;- ----------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;- ----------------------------------------------------------------------------
;- DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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;- ----------------------------------------------------------------------------
;- File Name : AT91SAM7S64.h
;- Object : AT91SAM7S64 definitions
;- Generated : AT91 SW Application Group 02/23/2005 (17:06:08)
;-
;- CVS Reference : /AT91SAM7S64.pl/1.18/Wed Feb 9 15:26:02 2005
;- CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005//
;- CVS Reference : /MC_SAM7S.pl/1.2/Tue Feb 1 17:01:00 2005//
;- CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005//
;- CVS Reference : /RSTC_SAM7S.pl/1.1/Tue Feb 1 16:16:35 2005//
;- CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
;- CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
;- CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
;- CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
;- CVS Reference : /UDP_6083C.pl/1.1/Mon Jan 31 13:01:46 2005//
;- CVS Reference : /AIC_6075A.pl/1.1/Fri Jun 28 10:36:48 2002//
;- CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
;- CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
;- CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
;- CVS Reference : /SPI_6088D.pl/1.2/Mon Feb 14 07:24:18 2005//
;- CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
;- CVS Reference : /TC_6082A.pl/1.6/Fri Feb 18 13:53:30 2005//
;- CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
;- CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
;- CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
;- CVS Reference : /PWM_6044D.pl/1.1/Tue Apr 27 14:53:52 2004//
;- ----------------------------------------------------------------------------
;- Hardware register definition
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR System Peripherals
;- *****************************************************************************
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
;- *****************************************************************************
^ 0 ;- AT91S_AIC
AIC_SMR # 128 ;- Source Mode Register
AIC_SVR # 128 ;- Source Vector Register
AIC_IVR # 4 ;- IRQ Vector Register
AIC_FVR # 4 ;- FIQ Vector Register
AIC_ISR # 4 ;- Interrupt Status Register
AIC_IPR # 4 ;- Interrupt Pending Register
AIC_IMR # 4 ;- Interrupt Mask Register
AIC_CISR # 4 ;- Core Interrupt Status Register
# 8 ;- Reserved
AIC_IECR # 4 ;- Interrupt Enable Command Register
AIC_IDCR # 4 ;- Interrupt Disable Command Register
AIC_ICCR # 4 ;- Interrupt Clear Command Register
AIC_ISCR # 4 ;- Interrupt Set Command Register
AIC_EOICR # 4 ;- End of Interrupt Command Register
AIC_SPU # 4 ;- Spurious Vector Register
AIC_DCR # 4 ;- Debug Control Register (Protect)
# 4 ;- Reserved
AIC_FFER # 4 ;- Fast Forcing Enable Register
AIC_FFDR # 4 ;- Fast Forcing Disable Register
AIC_FFSR # 4 ;- Fast Forcing Status Register
;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level
AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered
AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive
AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered
;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status
AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status
;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection Mode
AT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Peripheral DMA Controller
;- *****************************************************************************
^ 0 ;- AT91S_PDC
PDC_RPR # 4 ;- Receive Pointer Register
PDC_RCR # 4 ;- Receive Counter Register
PDC_TPR # 4 ;- Transmit Pointer Register
PDC_TCR # 4 ;- Transmit Counter Register
PDC_RNPR # 4 ;- Receive Next Pointer Register
PDC_RNCR # 4 ;- Receive Next Counter Register
PDC_TNPR # 4 ;- Transmit Next Pointer Register
PDC_TNCR # 4 ;- Transmit Next Counter Register
PDC_PTCR # 4 ;- PDC Transfer Control Register
PDC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable
AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable
AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable
AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable
;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Debug Unit
;- *****************************************************************************
^ 0 ;- AT91S_DBGU
DBGU_CR # 4 ;- Control Register
DBGU_MR # 4 ;- Mode Register
DBGU_IER # 4 ;- Interrupt Enable Register
DBGU_IDR # 4 ;- Interrupt Disable Register
DBGU_IMR # 4 ;- Interrupt Mask Register
DBGU_CSR # 4 ;- Channel Status Register
DBGU_RHR # 4 ;- Receiver Holding Register
DBGU_THR # 4 ;- Transmitter Holding Register
DBGU_BRGR # 4 ;- Baud Rate Generator Register
# 28 ;- Reserved
DBGU_CIDR # 4 ;- Chip ID Register
DBGU_EXID # 4 ;- Chip ID Extension Register
DBGU_FNTR # 4 ;- Force NTRST Register
# 180 ;- Reserved
DBGU_RPR # 4 ;- Receive Pointer Register
DBGU_RCR # 4 ;- Receive Counter Register
DBGU_TPR # 4 ;- Transmit Pointer Register
DBGU_TCR # 4 ;- Transmit Counter Register
DBGU_RNPR # 4 ;- Receive Next Pointer Register
DBGU_RNCR # 4 ;- Receive Next Counter Register
DBGU_TNPR # 4 ;- Transmit Next Pointer Register
DBGU_TNCR # 4 ;- Transmit Next Counter Register
DBGU_PTCR # 4 ;- PDC Transfer Control Register
DBGU_PTSR # 4 ;- PDC Transfer Status Register
;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver
AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter
AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable
AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable
AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable
AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable
AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (DBGU) Reset Status Bits
;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type
AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity
AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity
AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space)
AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark)
AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity
AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode
AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode
AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt
AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt
AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt
AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt
AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt
AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt
AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt
AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt
AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt
AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt
AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt
AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt
;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler
;- *****************************************************************************
^ 0 ;- AT91S_PIO
PIO_PER # 4 ;- PIO Enable Register
PIO_PDR # 4 ;- PIO Disable Register
PIO_PSR # 4 ;- PIO Status Register
# 4 ;- Reserved
PIO_OER # 4 ;- Output Enable Register
PIO_ODR # 4 ;- Output Disable Registerr
PIO_OSR # 4 ;- Output Status Register
# 4 ;- Reserved
PIO_IFER # 4 ;- Input Filter Enable Register
PIO_IFDR # 4 ;- Input Filter Disable Register
PIO_IFSR # 4 ;- Input Filter Status Register
# 4 ;- Reserved
PIO_SODR # 4 ;- Set Output Data Register
PIO_CODR # 4 ;- Clear Output Data Register
PIO_ODSR # 4 ;- Output Data Status Register
PIO_PDSR # 4 ;- Pin Data Status Register
PIO_IER # 4 ;- Interrupt Enable Register
PIO_IDR # 4 ;- Interrupt Disable Register
PIO_IMR # 4 ;- Interrupt Mask Register
PIO_ISR # 4 ;- Interrupt Status Register
PIO_MDER # 4 ;- Multi-driver Enable Register
PIO_MDDR # 4 ;- Multi-driver Disable Register
PIO_MDSR # 4 ;- Multi-driver Status Register
# 4 ;- Reserved
PIO_PPUDR # 4 ;- Pull-up Disable Register
PIO_PPUER # 4 ;- Pull-up Enable Register
PIO_PPUSR # 4 ;- Pull-up Status Register
# 4 ;- Reserved
PIO_ASR # 4 ;- Select A Register
PIO_BSR # 4 ;- Select B Register
PIO_ABSR # 4 ;- AB Select Status Register
# 36 ;- Reserved
PIO_OWER # 4 ;- Output Write Enable Register
PIO_OWDR # 4 ;- Output Write Disable Register
PIO_OWSR # 4 ;- Output Write Status Register
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Clock Generator Controler
;- *****************************************************************************
^ 0 ;- AT91S_CKGR
CKGR_MOR # 4 ;- Main Oscillator Register
CKGR_MCFR # 4 ;- Main Clock Frequency Register
# 4 ;- Reserved
CKGR_PLLR # 4 ;- PLL Register
;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
AT91C_CKGR_MOSCEN EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable
AT91C_CKGR_OSCBYPASS EQU (0x1:SHL:1) ;- (CKGR) Main Oscillator Bypass
AT91C_CKGR_OSCOUNT EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time
;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
AT91C_CKGR_MAINF EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency
AT91C_CKGR_MAINRDY EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready
;- -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
AT91C_CKGR_DIV EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected
AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0
AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed
AT91C_CKGR_PLLCOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL Counter
AT91C_CKGR_OUT EQU (0x3:SHL:14) ;- (CKGR) PLL Output Frequency Range
AT91C_CKGR_OUT_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
AT91C_CKGR_OUT_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
AT91C_CKGR_OUT_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
AT91C_CKGR_OUT_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
AT91C_CKGR_MUL EQU (0x7FF:SHL:16) ;- (CKGR) PLL Multiplier
AT91C_CKGR_USBDIV EQU (0x3:SHL:28) ;- (CKGR) Divider for USB Clocks
AT91C_CKGR_USBDIV_0 EQU (0x0:SHL:28) ;- (CKGR) Divider output is PLL clock output
AT91C_CKGR_USBDIV_1 EQU (0x1:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 2
AT91C_CKGR_USBDIV_2 EQU (0x2:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 4
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Power Management Controler
;- *****************************************************************************
^ 0 ;- AT91S_PMC
PMC_SCER # 4 ;- System Clock Enable Register
PMC_SCDR # 4 ;- System Clock Disable Register
PMC_SCSR # 4 ;- System Clock Status Register
# 4 ;- Reserved
PMC_PCER # 4 ;- Peripheral Clock Enable Register
PMC_PCDR # 4 ;- Peripheral Clock Disable Register
PMC_PCSR # 4 ;- Peripheral Clock Status Register
# 4 ;- Reserved
PMC_MOR # 4 ;- Main Oscillator Register
PMC_MCFR # 4 ;- Main Clock Frequency Register
# 4 ;- Reserved
PMC_PLLR # 4 ;- PLL Register
PMC_MCKR # 4 ;- Master Clock Register
# 12 ;- Reserved
PMC_PCKR # 12 ;- Programmable Clock Register
# 20 ;- Reserved
PMC_IER # 4 ;- Interrupt Enable Register
PMC_IDR # 4 ;- Interrupt Disable Register
PMC_SR # 4 ;- Status Register
PMC_IMR # 4 ;- Interrupt Mask Register
;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
AT91C_PMC_PCK EQU (0x1:SHL:0) ;- (PMC) Processor Clock
AT91C_PMC_UDP EQU (0x1:SHL:7) ;- (PMC) USB Device Port Clock
AT91C_PMC_PCK0 EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output
AT91C_PMC_PCK1 EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output
AT91C_PMC_PCK2 EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output
;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
;- -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
;- -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
;- -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
AT91C_PMC_CSS EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection
AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected
AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected
AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected
AT91C_PMC_PRES EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler
AT91C_PMC_PRES_CLK EQU (0x0:SHL:2) ;- (PMC) Selected clock
AT91C_PMC_PRES_CLK_2 EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2
AT91C_PMC_PRES_CLK_4 EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4
AT91C_PMC_PRES_CLK_8 EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8
AT91C_PMC_PRES_CLK_16 EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16
AT91C_PMC_PRES_CLK_32 EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32
AT91C_PMC_PRES_CLK_64 EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64
;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
AT91C_PMC_MOSCS EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask
AT91C_PMC_LOCK EQU (0x1:SHL:2) ;- (PMC) PLL Status/Enable/Disable/Mask
AT91C_PMC_MCKRDY EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK0RDY EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK1RDY EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
AT91C_PMC_PCK2RDY EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Reset Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_RSTC
RSTC_RCR # 4 ;- Reset Control Register
RSTC_RSR # 4 ;- Reset Status Register
RSTC_RMR # 4 ;- Reset Mode Register
;- -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
AT91C_RSTC_PROCRST EQU (0x1:SHL:0) ;- (RSTC) Processor Reset
AT91C_RSTC_PERRST EQU (0x1:SHL:2) ;- (RSTC) Peripheral Reset
AT91C_RSTC_EXTRST EQU (0x1:SHL:3) ;- (RSTC) External Reset
AT91C_RSTC_KEY EQU (0xFF:SHL:24) ;- (RSTC) Password
;- -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
AT91C_RSTC_URSTS EQU (0x1:SHL:0) ;- (RSTC) User Reset Status
AT91C_RSTC_BODSTS EQU (0x1:SHL:1) ;- (RSTC) Brownout Detection Status
AT91C_RSTC_RSTTYP EQU (0x7:SHL:8) ;- (RSTC) Reset Type
AT91C_RSTC_RSTTYP_POWERUP EQU (0x0:SHL:8) ;- (RSTC) Power-up Reset. VDDCORE rising.
AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1:SHL:8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2:SHL:8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3:SHL:8) ;- (RSTC) Software Reset. Processor reset required by the software.
AT91C_RSTC_RSTTYP_USER EQU (0x4:SHL:8) ;- (RSTC) User Reset. NRST pin detected low.
AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5:SHL:8) ;- (RSTC) Brownout Reset occured.
AT91C_RSTC_NRSTL EQU (0x1:SHL:16) ;- (RSTC) NRST pin level
AT91C_RSTC_SRCMP EQU (0x1:SHL:17) ;- (RSTC) Software Reset Command in Progress.
;- -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
AT91C_RSTC_URSTEN EQU (0x1:SHL:0) ;- (RSTC) User Reset Enable
AT91C_RSTC_URSTIEN EQU (0x1:SHL:4) ;- (RSTC) User Reset Interrupt Enable
AT91C_RSTC_ERSTL EQU (0xF:SHL:8) ;- (RSTC) User Reset Enable
AT91C_RSTC_BODIEN EQU (0x1:SHL:16) ;- (RSTC) Brownout Detection Interrupt Enable
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_RTTC
RTTC_RTMR # 4 ;- Real-time Mode Register
RTTC_RTAR # 4 ;- Real-time Alarm Register
RTTC_RTVR # 4 ;- Real-time Value Register
RTTC_RTSR # 4 ;- Real-time Status Register
;- -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
AT91C_RTTC_RTPRES EQU (0xFFFF:SHL:0) ;- (RTTC) Real-time Timer Prescaler Value
AT91C_RTTC_ALMIEN EQU (0x1:SHL:16) ;- (RTTC) Alarm Interrupt Enable
AT91C_RTTC_RTTINCIEN EQU (0x1:SHL:17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
AT91C_RTTC_RTTRST EQU (0x1:SHL:18) ;- (RTTC) Real Time Timer Restart
;- -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
AT91C_RTTC_ALMV EQU (0x0:SHL:0) ;- (RTTC) Alarm Value
;- -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
AT91C_RTTC_CRTV EQU (0x0:SHL:0) ;- (RTTC) Current Real-time Value
;- -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
AT91C_RTTC_ALMS EQU (0x1:SHL:0) ;- (RTTC) Real-time Alarm Status
AT91C_RTTC_RTTINC EQU (0x1:SHL:1) ;- (RTTC) Real-time Timer Increment
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_PITC
PITC_PIMR # 4 ;- Period Interval Mode Register
PITC_PISR # 4 ;- Period Interval Status Register
PITC_PIVR # 4 ;- Period Interval Value Register
PITC_PIIR # 4 ;- Period Interval Image Register
;- -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
AT91C_PITC_PIV EQU (0xFFFFF:SHL:0) ;- (PITC) Periodic Interval Value
AT91C_PITC_PITEN EQU (0x1:SHL:24) ;- (PITC) Periodic Interval Timer Enabled
AT91C_PITC_PITIEN EQU (0x1:SHL:25) ;- (PITC) Periodic Interval Timer Interrupt Enable
;- -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
AT91C_PITC_PITS EQU (0x1:SHL:0) ;- (PITC) Periodic Interval Timer Status
;- -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
AT91C_PITC_CPIV EQU (0xFFFFF:SHL:0) ;- (PITC) Current Periodic Interval Value
AT91C_PITC_PICNT EQU (0xFFF:SHL:20) ;- (PITC) Periodic Interval Counter
;- -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_WDTC
WDTC_WDCR # 4 ;- Watchdog Control Register
WDTC_WDMR # 4 ;- Watchdog Mode Register
WDTC_WDSR # 4 ;- Watchdog Status Register
;- -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
AT91C_WDTC_WDRSTT EQU (0x1:SHL:0) ;- (WDTC) Watchdog Restart
AT91C_WDTC_KEY EQU (0xFF:SHL:24) ;- (WDTC) Watchdog KEY Password
;- -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
AT91C_WDTC_WDV EQU (0xFFF:SHL:0) ;- (WDTC) Watchdog Timer Restart
AT91C_WDTC_WDFIEN EQU (0x1:SHL:12) ;- (WDTC) Watchdog Fault Interrupt Enable
AT91C_WDTC_WDRSTEN EQU (0x1:SHL:13) ;- (WDTC) Watchdog Reset Enable
AT91C_WDTC_WDRPROC EQU (0x1:SHL:14) ;- (WDTC) Watchdog Timer Restart
AT91C_WDTC_WDDIS EQU (0x1:SHL:15) ;- (WDTC) Watchdog Disable
AT91C_WDTC_WDD EQU (0xFFF:SHL:16) ;- (WDTC) Watchdog Delta Value
AT91C_WDTC_WDDBGHLT EQU (0x1:SHL:28) ;- (WDTC) Watchdog Debug Halt
AT91C_WDTC_WDIDLEHLT EQU (0x1:SHL:29) ;- (WDTC) Watchdog Idle Halt
;- -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
AT91C_WDTC_WDUNF EQU (0x1:SHL:0) ;- (WDTC) Watchdog Underflow
AT91C_WDTC_WDERR EQU (0x1:SHL:1) ;- (WDTC) Watchdog Error
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_VREG
VREG_MR # 4 ;- Voltage Regulator Mode Register
;- -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
AT91C_VREG_PSTDBY EQU (0x1:SHL:0) ;- (VREG) Voltage Regulator Power Standby Mode
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Memory Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_MC
MC_RCR # 4 ;- MC Remap Control Register
MC_ASR # 4 ;- MC Abort Status Register
MC_AASR # 4 ;- MC Abort Address Status Register
# 84 ;- Reserved
MC_FMR # 4 ;- MC Flash Mode Register
MC_FCR # 4 ;- MC Flash Command Register
MC_FSR # 4 ;- MC Flash Status Register
;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit
;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status
AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status
AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status
AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte
AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word
AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word
AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status
AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read
AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write
AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch
AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source
AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source
AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source
AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source
;- -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
AT91C_MC_FRDY EQU (0x1:SHL:0) ;- (MC) Flash Ready
AT91C_MC_LOCKE EQU (0x1:SHL:2) ;- (MC) Lock Error
AT91C_MC_PROGE EQU (0x1:SHL:3) ;- (MC) Programming Error
AT91C_MC_NEBP EQU (0x1:SHL:7) ;- (MC) No Erase Before Programming
AT91C_MC_FWS EQU (0x3:SHL:8) ;- (MC) Flash Wait State
AT91C_MC_FWS_0FWS EQU (0x0:SHL:8) ;- (MC) 1 cycle for Read, 2 for Write operations
AT91C_MC_FWS_1FWS EQU (0x1:SHL:8) ;- (MC) 2 cycles for Read, 3 for Write operations
AT91C_MC_FWS_2FWS EQU (0x2:SHL:8) ;- (MC) 3 cycles for Read, 4 for Write operations
AT91C_MC_FWS_3FWS EQU (0x3:SHL:8) ;- (MC) 4 cycles for Read, 4 for Write operations
AT91C_MC_FMCN EQU (0xFF:SHL:16) ;- (MC) Flash Microsecond Cycle Number
;- -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
AT91C_MC_FCMD EQU (0xF:SHL:0) ;- (MC) Flash Command
AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.
AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
AT91C_MC_PAGEN EQU (0x3FF:SHL:8) ;- (MC) Page Number
AT91C_MC_KEY EQU (0xFF:SHL:24) ;- (MC) Writing Protect Key
;- -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
AT91C_MC_SECURITY EQU (0x1:SHL:4) ;- (MC) Security Bit Status
AT91C_MC_GPNVM0 EQU (0x1:SHL:8) ;- (MC) Sector 0 Lock Status
AT91C_MC_GPNVM1 EQU (0x1:SHL:9) ;- (MC) Sector 1 Lock Status
AT91C_MC_GPNVM2 EQU (0x1:SHL:10) ;- (MC) Sector 2 Lock Status
AT91C_MC_GPNVM3 EQU (0x1:SHL:11) ;- (MC) Sector 3 Lock Status
AT91C_MC_GPNVM4 EQU (0x1:SHL:12) ;- (MC) Sector 4 Lock Status
AT91C_MC_GPNVM5 EQU (0x1:SHL:13) ;- (MC) Sector 5 Lock Status
AT91C_MC_GPNVM6 EQU (0x1:SHL:14) ;- (MC) Sector 6 Lock Status
AT91C_MC_GPNVM7 EQU (0x1:SHL:15) ;- (MC) Sector 7 Lock Status
AT91C_MC_LOCKS0 EQU (0x1:SHL:16) ;- (MC) Sector 0 Lock Status
AT91C_MC_LOCKS1 EQU (0x1:SHL:17) ;- (MC) Sector 1 Lock Status
AT91C_MC_LOCKS2 EQU (0x1:SHL:18) ;- (MC) Sector 2 Lock Status
AT91C_MC_LOCKS3 EQU (0x1:SHL:19) ;- (MC) Sector 3 Lock Status
AT91C_MC_LOCKS4 EQU (0x1:SHL:20) ;- (MC) Sector 4 Lock Status
AT91C_MC_LOCKS5 EQU (0x1:SHL:21) ;- (MC) Sector 5 Lock Status
AT91C_MC_LOCKS6 EQU (0x1:SHL:22) ;- (MC) Sector 6 Lock Status
AT91C_MC_LOCKS7 EQU (0x1:SHL:23) ;- (MC) Sector 7 Lock Status
AT91C_MC_LOCKS8 EQU (0x1:SHL:24) ;- (MC) Sector 8 Lock Status
AT91C_MC_LOCKS9 EQU (0x1:SHL:25) ;- (MC) Sector 9 Lock Status
AT91C_MC_LOCKS10 EQU (0x1:SHL:26) ;- (MC) Sector 10 Lock Status
AT91C_MC_LOCKS11 EQU (0x1:SHL:27) ;- (MC) Sector 11 Lock Status
AT91C_MC_LOCKS12 EQU (0x1:SHL:28) ;- (MC) Sector 12 Lock Status
AT91C_MC_LOCKS13 EQU (0x1:SHL:29) ;- (MC) Sector 13 Lock Status
AT91C_MC_LOCKS14 EQU (0x1:SHL:30) ;- (MC) Sector 14 Lock Status
AT91C_MC_LOCKS15 EQU (0x1:SHL:31) ;- (MC) Sector 15 Lock Status
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Serial Parallel Interface
;- *****************************************************************************
^ 0 ;- AT91S_SPI
SPI_CR # 4 ;- Control Register
SPI_MR # 4 ;- Mode Register
SPI_RDR # 4 ;- Receive Data Register
SPI_TDR # 4 ;- Transmit Data Register
SPI_SR # 4 ;- Status Register
SPI_IER # 4 ;- Interrupt Enable Register
SPI_IDR # 4 ;- Interrupt Disable Register
SPI_IMR # 4 ;- Interrupt Mask Register
# 16 ;- Reserved
SPI_CSR # 16 ;- Chip Select Register
# 192 ;- Reserved
SPI_RPR # 4 ;- Receive Pointer Register
SPI_RCR # 4 ;- Receive Counter Register
SPI_TPR # 4 ;- Transmit Pointer Register
SPI_TCR # 4 ;- Transmit Counter Register
SPI_RNPR # 4 ;- Receive Next Pointer Register
SPI_RNCR # 4 ;- Receive Next Counter Register
SPI_TNPR # 4 ;- Transmit Next Pointer Register
SPI_TNCR # 4 ;- Transmit Next Counter Register
SPI_PTCR # 4 ;- PDC Transfer Control Register
SPI_PTSR # 4 ;- PDC Transfer Status Register
;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI Enable
AT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI Disable
AT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset
AT91C_SPI_LASTXFER EQU (0x1:SHL:24) ;- (SPI) SPI Last Transfer
;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode
AT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral Select
AT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select
AT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select
AT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode
AT91C_SPI_FDIV EQU (0x1:SHL:3) ;- (SPI) Clock Selection
AT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection
AT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock Selection
AT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select
AT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects
;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data
AT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data
AT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
;- -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full
AT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty
AT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error
AT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status
AT91C_SPI_ENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer
AT91C_SPI_ENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer
AT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt
AT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt
AT91C_SPI_NSSR EQU (0x1:SHL:8) ;- (SPI) NSSR Interrupt
AT91C_SPI_TXEMPTY EQU (0x1:SHL:9) ;- (SPI) TXEMPTY Interrupt
AT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status
;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock Polarity
AT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock Phase
AT91C_SPI_CSAAT EQU (0x1:SHL:3) ;- (SPI) Chip Select Active After Transfer
AT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer
AT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer
AT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer
AT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer
AT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer
AT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer
AT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer
AT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer
AT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer
AT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer
AT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate
AT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Serial Clock Baud Rate
AT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Analog to Digital Convertor
;- *****************************************************************************
^ 0 ;- AT91S_ADC
ADC_CR # 4 ;- ADC Control Register
ADC_MR # 4 ;- ADC Mode Register
# 8 ;- Reserved
ADC_CHER # 4 ;- ADC Channel Enable Register
ADC_CHDR # 4 ;- ADC Channel Disable Register
ADC_CHSR # 4 ;- ADC Channel Status Register
ADC_SR # 4 ;- ADC Status Register
ADC_LCDR # 4 ;- ADC Last Converted Data Register
ADC_IER # 4 ;- ADC Interrupt Enable Register
ADC_IDR # 4 ;- ADC Interrupt Disable Register
ADC_IMR # 4 ;- ADC Interrupt Mask Register
ADC_CDR0 # 4 ;- ADC Channel Data Register 0
ADC_CDR1 # 4 ;- ADC Channel Data Register 1
ADC_CDR2 # 4 ;- ADC Channel Data Register 2
ADC_CDR3 # 4 ;- ADC Channel Data Register 3
ADC_CDR4 # 4 ;- ADC Channel Data Register 4
ADC_CDR5 # 4 ;- ADC Channel Data Register 5
ADC_CDR6 # 4 ;- ADC Channel Data Register 6
ADC_CDR7 # 4 ;- ADC Channel Data Register 7
# 176 ;- Reserved
ADC_RPR # 4 ;- Receive Pointer Register
ADC_RCR # 4 ;- Receive Counter Register
ADC_TPR # 4 ;- Transmit Pointer Register
ADC_TCR # 4 ;- Transmit Counter Register
ADC_RNPR # 4 ;- Receive Next Pointer Register
ADC_RNCR # 4 ;- Receive Next Counter Register
ADC_TNPR # 4 ;- Transmit Next Pointer Register
ADC_TNCR # 4 ;- Transmit Next Counter Register
ADC_PTCR # 4 ;- PDC Transfer Control Register
ADC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
AT91C_ADC_SWRST EQU (0x1:SHL:0) ;- (ADC) Software Reset
AT91C_ADC_START EQU (0x1:SHL:1) ;- (ADC) Start Conversion
;- -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
AT91C_ADC_TRGEN EQU (0x1:SHL:0) ;- (ADC) Trigger Enable
AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
AT91C_ADC_TRGSEL EQU (0x7:SHL:1) ;- (ADC) Trigger Selection
AT91C_ADC_TRGSEL_TIOA0 EQU (0x0:SHL:1) ;- (ADC) Selected TRGSEL = TIAO0
AT91C_ADC_TRGSEL_TIOA1 EQU (0x1:SHL:1) ;- (ADC) Selected TRGSEL = TIAO1
AT91C_ADC_TRGSEL_TIOA2 EQU (0x2:SHL:1) ;- (ADC) Selected TRGSEL = TIAO2
AT91C_ADC_TRGSEL_TIOA3 EQU (0x3:SHL:1) ;- (ADC) Selected TRGSEL = TIAO3
AT91C_ADC_TRGSEL_TIOA4 EQU (0x4:SHL:1) ;- (ADC) Selected TRGSEL = TIAO4
AT91C_ADC_TRGSEL_TIOA5 EQU (0x5:SHL:1) ;- (ADC) Selected TRGSEL = TIAO5
AT91C_ADC_TRGSEL_EXT EQU (0x6:SHL:1) ;- (ADC) Selected TRGSEL = External Trigger
AT91C_ADC_LOWRES EQU (0x1:SHL:4) ;- (ADC) Resolution.
AT91C_ADC_LOWRES_10_BIT EQU (0x0:SHL:4) ;- (ADC) 10-bit resolution
AT91C_ADC_LOWRES_8_BIT EQU (0x1:SHL:4) ;- (ADC) 8-bit resolution
AT91C_ADC_SLEEP EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0:SHL:5) ;- (ADC) Normal Mode
AT91C_ADC_SLEEP_MODE EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
AT91C_ADC_PRESCAL EQU (0x3F:SHL:8) ;- (ADC) Prescaler rate selection
AT91C_ADC_STARTUP EQU (0x1F:SHL:16) ;- (ADC) Startup Time
AT91C_ADC_SHTIM EQU (0xF:SHL:24) ;- (ADC) Sample & Hold Time
;- -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
AT91C_ADC_CH0 EQU (0x1:SHL:0) ;- (ADC) Channel 0
AT91C_ADC_CH1 EQU (0x1:SHL:1) ;- (ADC) Channel 1
AT91C_ADC_CH2 EQU (0x1:SHL:2) ;- (ADC) Channel 2
AT91C_ADC_CH3 EQU (0x1:SHL:3) ;- (ADC) Channel 3
AT91C_ADC_CH4 EQU (0x1:SHL:4) ;- (ADC) Channel 4
AT91C_ADC_CH5 EQU (0x1:SHL:5) ;- (ADC) Channel 5
AT91C_ADC_CH6 EQU (0x1:SHL:6) ;- (ADC) Channel 6
AT91C_ADC_CH7 EQU (0x1:SHL:7) ;- (ADC) Channel 7
;- -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
;- -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
;- -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
AT91C_ADC_EOC0 EQU (0x1:SHL:0) ;- (ADC) End of Conversion
AT91C_ADC_EOC1 EQU (0x1:SHL:1) ;- (ADC) End of Conversion
AT91C_ADC_EOC2 EQU (0x1:SHL:2) ;- (ADC) End of Conversion
AT91C_ADC_EOC3 EQU (0x1:SHL:3) ;- (ADC) End of Conversion
AT91C_ADC_EOC4 EQU (0x1:SHL:4) ;- (ADC) End of Conversion
AT91C_ADC_EOC5 EQU (0x1:SHL:5) ;- (ADC) End of Conversion
AT91C_ADC_EOC6 EQU (0x1:SHL:6) ;- (ADC) End of Conversion
AT91C_ADC_EOC7 EQU (0x1:SHL:7) ;- (ADC) End of Conversion
AT91C_ADC_OVRE0 EQU (0x1:SHL:8) ;- (ADC) Overrun Error
AT91C_ADC_OVRE1 EQU (0x1:SHL:9) ;- (ADC) Overrun Error
AT91C_ADC_OVRE2 EQU (0x1:SHL:10) ;- (ADC) Overrun Error
AT91C_ADC_OVRE3 EQU (0x1:SHL:11) ;- (ADC) Overrun Error
AT91C_ADC_OVRE4 EQU (0x1:SHL:12) ;- (ADC) Overrun Error
AT91C_ADC_OVRE5 EQU (0x1:SHL:13) ;- (ADC) Overrun Error
AT91C_ADC_OVRE6 EQU (0x1:SHL:14) ;- (ADC) Overrun Error
AT91C_ADC_OVRE7 EQU (0x1:SHL:15) ;- (ADC) Overrun Error
AT91C_ADC_DRDY EQU (0x1:SHL:16) ;- (ADC) Data Ready
AT91C_ADC_GOVRE EQU (0x1:SHL:17) ;- (ADC) General Overrun
AT91C_ADC_ENDRX EQU (0x1:SHL:18) ;- (ADC) End of Receiver Transfer
AT91C_ADC_RXBUFF EQU (0x1:SHL:19) ;- (ADC) RXBUFF Interrupt
;- -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
AT91C_ADC_LDATA EQU (0x3FF:SHL:0) ;- (ADC) Last Data Converted
;- -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
;- -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
;- -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
;- -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
AT91C_ADC_DATA EQU (0x3FF:SHL:0) ;- (ADC) Converted Data
;- -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
;- -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
;- -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
;- -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
;- -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
;- -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
;- -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_SSC
SSC_CR # 4 ;- Control Register
SSC_CMR # 4 ;- Clock Mode Register
# 8 ;- Reserved
SSC_RCMR # 4 ;- Receive Clock ModeRegister
SSC_RFMR # 4 ;- Receive Frame Mode Register
SSC_TCMR # 4 ;- Transmit Clock Mode Register
SSC_TFMR # 4 ;- Transmit Frame Mode Register
SSC_RHR # 4 ;- Receive Holding Register
SSC_THR # 4 ;- Transmit Holding Register
# 8 ;- Reserved
SSC_RSHR # 4 ;- Receive Sync Holding Register
SSC_TSHR # 4 ;- Transmit Sync Holding Register
# 8 ;- Reserved
SSC_SR # 4 ;- Status Register
SSC_IER # 4 ;- Interrupt Enable Register
SSC_IDR # 4 ;- Interrupt Disable Register
SSC_IMR # 4 ;- Interrupt Mask Register
# 176 ;- Reserved
SSC_RPR # 4 ;- Receive Pointer Register
SSC_RCR # 4 ;- Receive Counter Register
SSC_TPR # 4 ;- Transmit Pointer Register
SSC_TCR # 4 ;- Transmit Counter Register
SSC_RNPR # 4 ;- Receive Next Pointer Register
SSC_RNCR # 4 ;- Receive Next Counter Register
SSC_TNPR # 4 ;- Transmit Next Pointer Register
SSC_TNCR # 4 ;- Transmit Next Counter Register
SSC_PTCR # 4 ;- PDC Transfer Control Register
SSC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive Enable
AT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable
AT91C_SSC_TXEN EQU (0x1:SHL:8) ;- (SSC) Transmit Enable
AT91C_SSC_TXDIS EQU (0x1:SHL:9) ;- (SSC) Transmit Disable
AT91C_SSC_SWRST EQU (0x1:SHL:15) ;- (SSC) Software Reset
;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
AT91C_SSC_CKS EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection
AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
AT91C_SSC_CKO EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
AT91C_SSC_CKO_NONE EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
AT91C_SSC_CKO_CONTINOUS EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
AT91C_SSC_CKO_DATA_TX EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
AT91C_SSC_CKI EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion
AT91C_SSC_START EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection
AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
AT91C_SSC_START_TX EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start
AT91C_SSC_START_LOW_RF EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input
AT91C_SSC_START_HIGH_RF EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input
AT91C_SSC_START_FALL_RF EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input
AT91C_SSC_START_RISE_RF EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input
AT91C_SSC_START_LEVEL_RF EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input
AT91C_SSC_START_EDGE_RF EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input
AT91C_SSC_START_0 EQU (0x8:SHL:8) ;- (SSC) Compare 0
AT91C_SSC_STTDLY EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay
AT91C_SSC_PERIOD EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection
;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
AT91C_SSC_DATLEN EQU (0x1F:SHL:0) ;- (SSC) Data Length
AT91C_SSC_LOOP EQU (0x1:SHL:5) ;- (SSC) Loop Mode
AT91C_SSC_MSBF EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First
AT91C_SSC_DATNB EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame
AT91C_SSC_FSLEN EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length
AT91C_SSC_FSOS EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
AT91C_SSC_FSOS_NONE EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
AT91C_SSC_FSOS_NEGATIVE EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
AT91C_SSC_FSOS_POSITIVE EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
AT91C_SSC_FSOS_LOW EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
AT91C_SSC_FSOS_HIGH EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
AT91C_SSC_FSOS_TOGGLE EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
AT91C_SSC_FSEDGE EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection
;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
AT91C_SSC_DATDEF EQU (0x1:SHL:5) ;- (SSC) Data Default Value
AT91C_SSC_FSDEN EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable
;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
AT91C_SSC_TXRDY EQU (0x1:SHL:0) ;- (SSC) Transmit Ready
AT91C_SSC_TXEMPTY EQU (0x1:SHL:1) ;- (SSC) Transmit Empty
AT91C_SSC_ENDTX EQU (0x1:SHL:2) ;- (SSC) End Of Transmission
AT91C_SSC_TXBUFE EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty
AT91C_SSC_RXRDY EQU (0x1:SHL:4) ;- (SSC) Receive Ready
AT91C_SSC_OVRUN EQU (0x1:SHL:5) ;- (SSC) Receive Overrun
AT91C_SSC_ENDRX EQU (0x1:SHL:6) ;- (SSC) End of Reception
AT91C_SSC_RXBUFF EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full
AT91C_SSC_TXSYN EQU (0x1:SHL:10) ;- (SSC) Transmit Sync
AT91C_SSC_RXSYN EQU (0x1:SHL:11) ;- (SSC) Receive Sync
AT91C_SSC_TXENA EQU (0x1:SHL:16) ;- (SSC) Transmit Enable
AT91C_SSC_RXENA EQU (0x1:SHL:17) ;- (SSC) Receive Enable
;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Usart
;- *****************************************************************************
^ 0 ;- AT91S_USART
US_CR # 4 ;- Control Register
US_MR # 4 ;- Mode Register
US_IER # 4 ;- Interrupt Enable Register
US_IDR # 4 ;- Interrupt Disable Register
US_IMR # 4 ;- Interrupt Mask Register
US_CSR # 4 ;- Channel Status Register
US_RHR # 4 ;- Receiver Holding Register
US_THR # 4 ;- Transmitter Holding Register
US_BRGR # 4 ;- Baud Rate Generator Register
US_RTOR # 4 ;- Receiver Time-out Register
US_TTGR # 4 ;- Transmitter Time-guard Register
# 20 ;- Reserved
US_FIDI # 4 ;- FI_DI_Ratio Register
US_NER # 4 ;- Nb Errors Register
# 4 ;- Reserved
US_IF # 4 ;- IRDA_FILTER Register
# 176 ;- Reserved
US_RPR # 4 ;- Receive Pointer Register
US_RCR # 4 ;- Receive Counter Register
US_TPR # 4 ;- Transmit Pointer Register
US_TCR # 4 ;- Transmit Counter Register
US_RNPR # 4 ;- Receive Next Pointer Register
US_RNCR # 4 ;- Receive Next Counter Register
US_TNPR # 4 ;- Transmit Next Pointer Register
US_TNCR # 4 ;- Transmit Next Counter Register
US_PTCR # 4 ;- PDC Transfer Control Register
US_PTSR # 4 ;- PDC Transfer Status Register
;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break
AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break
AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out
AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address
AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations
AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge
AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out
AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable
AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable
AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable
AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable
;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode
AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock
AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1
AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)
AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK)
AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits
AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits
AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits
AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits
AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select
AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits
AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit
AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits
AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order
AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length
AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select
AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode
AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge
AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK
AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions
AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter
;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break
AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out
AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached
AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge
AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag
AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag
AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag
AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag
;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input
AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input
AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input
AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Two-wire Interface
;- *****************************************************************************
^ 0 ;- AT91S_TWI
TWI_CR # 4 ;- Control Register
TWI_MMR # 4 ;- Master Mode Register
# 4 ;- Reserved
TWI_IADR # 4 ;- Internal Address Register
TWI_CWGR # 4 ;- Clock Waveform Generator Register
# 12 ;- Reserved
TWI_SR # 4 ;- Status Register
TWI_IER # 4 ;- Interrupt Enable Register
TWI_IDR # 4 ;- Interrupt Disable Register
TWI_IMR # 4 ;- Interrupt Mask Register
TWI_RHR # 4 ;- Receive Holding Register
TWI_THR # 4 ;- Transmit Holding Register
;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
AT91C_TWI_START EQU (0x1:SHL:0) ;- (TWI) Send a START Condition
AT91C_TWI_STOP EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition
AT91C_TWI_MSEN EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled
AT91C_TWI_MSDIS EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled
AT91C_TWI_SWRST EQU (0x1:SHL:7) ;- (TWI) Software Reset
;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
AT91C_TWI_IADRSZ EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size
AT91C_TWI_IADRSZ_NO EQU (0x0:SHL:8) ;- (TWI) No internal device address
AT91C_TWI_IADRSZ_1_BYTE EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address
AT91C_TWI_IADRSZ_2_BYTE EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address
AT91C_TWI_IADRSZ_3_BYTE EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address
AT91C_TWI_MREAD EQU (0x1:SHL:12) ;- (TWI) Master Read Direction
AT91C_TWI_DADR EQU (0x7F:SHL:16) ;- (TWI) Device Address
;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
AT91C_TWI_CLDIV EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider
AT91C_TWI_CHDIV EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider
AT91C_TWI_CKDIV EQU (0x7:SHL:16) ;- (TWI) Clock Divider
;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
AT91C_TWI_TXCOMP EQU (0x1:SHL:0) ;- (TWI) Transmission Completed
AT91C_TWI_RXRDY EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY
AT91C_TWI_TXRDY EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY
AT91C_TWI_OVRE EQU (0x1:SHL:6) ;- (TWI) Overrun Error
AT91C_TWI_UNRE EQU (0x1:SHL:7) ;- (TWI) Underrun Error
AT91C_TWI_NACK EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged
;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
;- *****************************************************************************
^ 0 ;- AT91S_TC
TC_CCR # 4 ;- Channel Control Register
TC_CMR # 4 ;- Channel Mode Register (Capture Mode / Waveform Mode)
# 8 ;- Reserved
TC_CV # 4 ;- Counter Value
TC_RA # 4 ;- Register A
TC_RB # 4 ;- Register B
TC_RC # 4 ;- Register C
TC_SR # 4 ;- Status Register
TC_IER # 4 ;- Interrupt Enable Register
TC_IDR # 4 ;- Interrupt Disable Register
TC_IMR # 4 ;- Interrupt Mask Register
;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
AT91C_TC_CLKEN EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command
AT91C_TC_CLKDIS EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command
AT91C_TC_SWTRG EQU (0x1:SHL:2) ;- (TC) Software Trigger Command
;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
AT91C_TC_CLKS EQU (0x7:SHL:0) ;- (TC) Clock Selection
AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0
AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1
AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2
AT91C_TC_CLKI EQU (0x1:SHL:3) ;- (TC) Clock Invert
AT91C_TC_BURST EQU (0x3:SHL:4) ;- (TC) Burst Signal Selection
AT91C_TC_BURST_NONE EQU (0x0:SHL:4) ;- (TC) The clock is not gated by an external signal
AT91C_TC_BURST_XC0 EQU (0x1:SHL:4) ;- (TC) XC0 is ANDed with the selected clock
AT91C_TC_BURST_XC1 EQU (0x2:SHL:4) ;- (TC) XC1 is ANDed with the selected clock
AT91C_TC_BURST_XC2 EQU (0x3:SHL:4) ;- (TC) XC2 is ANDed with the selected clock
AT91C_TC_CPCSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare
AT91C_TC_LDBSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RB Loading
AT91C_TC_CPCDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare
AT91C_TC_LDBDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disabled with RB Loading
AT91C_TC_ETRGEDG EQU (0x3:SHL:8) ;- (TC) External Trigger Edge Selection
AT91C_TC_ETRGEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None
AT91C_TC_ETRGEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
AT91C_TC_ETRGEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
AT91C_TC_ETRGEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge
AT91C_TC_EEVTEDG EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection
AT91C_TC_EEVTEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None
AT91C_TC_EEVTEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
AT91C_TC_EEVTEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
AT91C_TC_EEVTEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge
AT91C_TC_EEVT EQU (0x3:SHL:10) ;- (TC) External Event Selection
AT91C_TC_EEVT_TIOB EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
AT91C_TC_EEVT_XC0 EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
AT91C_TC_EEVT_XC1 EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
AT91C_TC_EEVT_XC2 EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
AT91C_TC_ABETRG EQU (0x1:SHL:10) ;- (TC) TIOA or TIOB External Trigger Selection
AT91C_TC_ENETRG EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable
AT91C_TC_WAVESEL EQU (0x3:SHL:13) ;- (TC) Waveform Selection
AT91C_TC_WAVESEL_UP EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare
AT91C_TC_WAVESEL_UPDOWN EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
AT91C_TC_WAVESEL_UP_AUTO EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare
AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
AT91C_TC_CPCTRG EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable
AT91C_TC_WAVE EQU (0x1:SHL:15) ;- (TC)
AT91C_TC_ACPA EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA
AT91C_TC_ACPA_NONE EQU (0x0:SHL:16) ;- (TC) Effect: none
AT91C_TC_ACPA_SET EQU (0x1:SHL:16) ;- (TC) Effect: set
AT91C_TC_ACPA_CLEAR EQU (0x2:SHL:16) ;- (TC) Effect: clear
AT91C_TC_ACPA_TOGGLE EQU (0x3:SHL:16) ;- (TC) Effect: toggle
AT91C_TC_LDRA EQU (0x3:SHL:16) ;- (TC) RA Loading Selection
AT91C_TC_LDRA_NONE EQU (0x0:SHL:16) ;- (TC) Edge: None
AT91C_TC_LDRA_RISING EQU (0x1:SHL:16) ;- (TC) Edge: rising edge of TIOA
AT91C_TC_LDRA_FALLING EQU (0x2:SHL:16) ;- (TC) Edge: falling edge of TIOA
AT91C_TC_LDRA_BOTH EQU (0x3:SHL:16) ;- (TC) Edge: each edge of TIOA
AT91C_TC_ACPC EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA
AT91C_TC_ACPC_NONE EQU (0x0:SHL:18) ;- (TC) Effect: none
AT91C_TC_ACPC_SET EQU (0x1:SHL:18) ;- (TC) Effect: set
AT91C_TC_ACPC_CLEAR EQU (0x2:SHL:18) ;- (TC) Effect: clear
AT91C_TC_ACPC_TOGGLE EQU (0x3:SHL:18) ;- (TC) Effect: toggle
AT91C_TC_LDRB EQU (0x3:SHL:18) ;- (TC) RB Loading Selection
AT91C_TC_LDRB_NONE EQU (0x0:SHL:18) ;- (TC) Edge: None
AT91C_TC_LDRB_RISING EQU (0x1:SHL:18) ;- (TC) Edge: rising edge of TIOA
AT91C_TC_LDRB_FALLING EQU (0x2:SHL:18) ;- (TC) Edge: falling edge of TIOA
AT91C_TC_LDRB_BOTH EQU (0x3:SHL:18) ;- (TC) Edge: each edge of TIOA
AT91C_TC_AEEVT EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA
AT91C_TC_AEEVT_NONE EQU (0x0:SHL:20) ;- (TC) Effect: none
AT91C_TC_AEEVT_SET EQU (0x1:SHL:20) ;- (TC) Effect: set
AT91C_TC_AEEVT_CLEAR EQU (0x2:SHL:20) ;- (TC) Effect: clear
AT91C_TC_AEEVT_TOGGLE EQU (0x3:SHL:20) ;- (TC) Effect: toggle
AT91C_TC_ASWTRG EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA
AT91C_TC_ASWTRG_NONE EQU (0x0:SHL:22) ;- (TC) Effect: none
AT91C_TC_ASWTRG_SET EQU (0x1:SHL:22) ;- (TC) Effect: set
AT91C_TC_ASWTRG_CLEAR EQU (0x2:SHL:22) ;- (TC) Effect: clear
AT91C_TC_ASWTRG_TOGGLE EQU (0x3:SHL:22) ;- (TC) Effect: toggle
AT91C_TC_BCPB EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB
AT91C_TC_BCPB_NONE EQU (0x0:SHL:24) ;- (TC) Effect: none
AT91C_TC_BCPB_SET EQU (0x1:SHL:24) ;- (TC) Effect: set
AT91C_TC_BCPB_CLEAR EQU (0x2:SHL:24) ;- (TC) Effect: clear
AT91C_TC_BCPB_TOGGLE EQU (0x3:SHL:24) ;- (TC) Effect: toggle
AT91C_TC_BCPC EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB
AT91C_TC_BCPC_NONE EQU (0x0:SHL:26) ;- (TC) Effect: none
AT91C_TC_BCPC_SET EQU (0x1:SHL:26) ;- (TC) Effect: set
AT91C_TC_BCPC_CLEAR EQU (0x2:SHL:26) ;- (TC) Effect: clear
AT91C_TC_BCPC_TOGGLE EQU (0x3:SHL:26) ;- (TC) Effect: toggle
AT91C_TC_BEEVT EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB
AT91C_TC_BEEVT_NONE EQU (0x0:SHL:28) ;- (TC) Effect: none
AT91C_TC_BEEVT_SET EQU (0x1:SHL:28) ;- (TC) Effect: set
AT91C_TC_BEEVT_CLEAR EQU (0x2:SHL:28) ;- (TC) Effect: clear
AT91C_TC_BEEVT_TOGGLE EQU (0x3:SHL:28) ;- (TC) Effect: toggle
AT91C_TC_BSWTRG EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB
AT91C_TC_BSWTRG_NONE EQU (0x0:SHL:30) ;- (TC) Effect: none
AT91C_TC_BSWTRG_SET EQU (0x1:SHL:30) ;- (TC) Effect: set
AT91C_TC_BSWTRG_CLEAR EQU (0x2:SHL:30) ;- (TC) Effect: clear
AT91C_TC_BSWTRG_TOGGLE EQU (0x3:SHL:30) ;- (TC) Effect: toggle
;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
AT91C_TC_COVFS EQU (0x1:SHL:0) ;- (TC) Counter Overflow
AT91C_TC_LOVRS EQU (0x1:SHL:1) ;- (TC) Load Overrun
AT91C_TC_CPAS EQU (0x1:SHL:2) ;- (TC) RA Compare
AT91C_TC_CPBS EQU (0x1:SHL:3) ;- (TC) RB Compare
AT91C_TC_CPCS EQU (0x1:SHL:4) ;- (TC) RC Compare
AT91C_TC_LDRAS EQU (0x1:SHL:5) ;- (TC) RA Loading
AT91C_TC_LDRBS EQU (0x1:SHL:6) ;- (TC) RB Loading
AT91C_TC_ETRGS EQU (0x1:SHL:7) ;- (TC) External Trigger
AT91C_TC_CLKSTA EQU (0x1:SHL:16) ;- (TC) Clock Enabling
AT91C_TC_MTIOA EQU (0x1:SHL:17) ;- (TC) TIOA Mirror
AT91C_TC_MTIOB EQU (0x1:SHL:18) ;- (TC) TIOA Mirror
;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Timer Counter Interface
;- *****************************************************************************
^ 0 ;- AT91S_TCB
TCB_TC0 # 48 ;- TC Channel 0
# 16 ;- Reserved
TCB_TC1 # 48 ;- TC Channel 1
# 16 ;- Reserved
TCB_TC2 # 48 ;- TC Channel 2
# 16 ;- Reserved
TCB_BCR # 4 ;- TC Block Control Register
TCB_BMR # 4 ;- TC Block Mode Register
;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
AT91C_TCB_SYNC EQU (0x1:SHL:0) ;- (TCB) Synchro Command
;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
AT91C_TCB_TC0XC0S EQU (0x3:SHL:0) ;- (TCB) External Clock Signal 0 Selection
AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0
AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0
AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0
AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0
AT91C_TCB_TC1XC1S EQU (0x3:SHL:2) ;- (TCB) External Clock Signal 1 Selection
AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1
AT91C_TCB_TC1XC1S_NONE EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1
AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1
AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1
AT91C_TCB_TC2XC2S EQU (0x3:SHL:4) ;- (TCB) External Clock Signal 2 Selection
AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2
AT91C_TCB_TC2XC2S_NONE EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2
AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2
AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR PWMC Channel Interface
;- *****************************************************************************
^ 0 ;- AT91S_PWMC_CH
PWMC_CMR # 4 ;- Channel Mode Register
PWMC_CDTYR # 4 ;- Channel Duty Cycle Register
PWMC_CPRDR # 4 ;- Channel Period Register
PWMC_CCNTR # 4 ;- Channel Counter Register
PWMC_CUPDR # 4 ;- Channel Update Register
PWMC_Reserved # 12 ;- Reserved
;- -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
AT91C_PWMC_CPRE EQU (0xF:SHL:0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH)
AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH)
AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH)
AT91C_PWMC_CALG EQU (0x1:SHL:8) ;- (PWMC_CH) Channel Alignment
AT91C_PWMC_CPOL EQU (0x1:SHL:9) ;- (PWMC_CH) Channel Polarity
AT91C_PWMC_CPD EQU (0x1:SHL:10) ;- (PWMC_CH) Channel Update Period
;- -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
AT91C_PWMC_CDTY EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Duty Cycle
;- -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
AT91C_PWMC_CPRD EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Period
;- -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
AT91C_PWMC_CCNT EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Counter
;- -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
AT91C_PWMC_CUPD EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Update
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_PWMC
PWMC_MR # 4 ;- PWMC Mode Register
PWMC_ENA # 4 ;- PWMC Enable Register
PWMC_DIS # 4 ;- PWMC Disable Register
PWMC_SR # 4 ;- PWMC Status Register
PWMC_IER # 4 ;- PWMC Interrupt Enable Register
PWMC_IDR # 4 ;- PWMC Interrupt Disable Register
PWMC_IMR # 4 ;- PWMC Interrupt Mask Register
PWMC_ISR # 4 ;- PWMC Interrupt Status Register
# 220 ;- Reserved
PWMC_VR # 4 ;- PWMC Version Register
# 256 ;- Reserved
PWMC_CH # 768 ;- PWMC Channel 0
;- -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
AT91C_PWMC_DIVA EQU (0xFF:SHL:0) ;- (PWMC) CLKA divide factor.
AT91C_PWMC_PREA EQU (0xF:SHL:8) ;- (PWMC) Divider Input Clock Prescaler A
AT91C_PWMC_PREA_MCK EQU (0x0:SHL:8) ;- (PWMC)
AT91C_PWMC_DIVB EQU (0xFF:SHL:16) ;- (PWMC) CLKB divide factor.
AT91C_PWMC_PREB EQU (0xF:SHL:24) ;- (PWMC) Divider Input Clock Prescaler B
AT91C_PWMC_PREB_MCK EQU (0x0:SHL:24) ;- (PWMC)
;- -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
AT91C_PWMC_CHID0 EQU (0x1:SHL:0) ;- (PWMC) Channel ID 0
AT91C_PWMC_CHID1 EQU (0x1:SHL:1) ;- (PWMC) Channel ID 1
AT91C_PWMC_CHID2 EQU (0x1:SHL:2) ;- (PWMC) Channel ID 2
AT91C_PWMC_CHID3 EQU (0x1:SHL:3) ;- (PWMC) Channel ID 3
AT91C_PWMC_CHID4 EQU (0x1:SHL:4) ;- (PWMC) Channel ID 4
AT91C_PWMC_CHID5 EQU (0x1:SHL:5) ;- (PWMC) Channel ID 5
AT91C_PWMC_CHID6 EQU (0x1:SHL:6) ;- (PWMC) Channel ID 6
AT91C_PWMC_CHID7 EQU (0x1:SHL:7) ;- (PWMC) Channel ID 7
;- -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
;- -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
;- -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
;- -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
;- -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
;- -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR USB Device Interface
;- *****************************************************************************
^ 0 ;- AT91S_UDP
UDP_NUM # 4 ;- Frame Number Register
UDP_GLBSTATE # 4 ;- Global State Register
UDP_FADDR # 4 ;- Function Address Register
# 4 ;- Reserved
UDP_IER # 4 ;- Interrupt Enable Register
UDP_IDR # 4 ;- Interrupt Disable Register
UDP_IMR # 4 ;- Interrupt Mask Register
UDP_ISR # 4 ;- Interrupt Status Register
UDP_ICR # 4 ;- Interrupt Clear Register
# 4 ;- Reserved
UDP_RSTEP # 4 ;- Reset Endpoint Register
# 4 ;- Reserved
UDP_CSR # 32 ;- Endpoint Control and Status Register
UDP_FDR # 32 ;- Endpoint FIFO Data Register
# 4 ;- Reserved
UDP_TXVC # 4 ;- Transceiver Control Register
;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
AT91C_UDP_FRM_NUM EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
AT91C_UDP_FRM_ERR EQU (0x1:SHL:16) ;- (UDP) Frame Error
AT91C_UDP_FRM_OK EQU (0x1:SHL:17) ;- (UDP) Frame OK
;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
AT91C_UDP_FADDEN EQU (0x1:SHL:0) ;- (UDP) Function Address Enable
AT91C_UDP_CONFG EQU (0x1:SHL:1) ;- (UDP) Configured
AT91C_UDP_ESR EQU (0x1:SHL:2) ;- (UDP) Enable Send Resume
AT91C_UDP_RSMINPR EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host
AT91C_UDP_RMWUPE EQU (0x1:SHL:4) ;- (UDP) Remote Wake Up Enable
;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
AT91C_UDP_FADD EQU (0xFF:SHL:0) ;- (UDP) Function Address Value
AT91C_UDP_FEN EQU (0x1:SHL:8) ;- (UDP) Function Enable
;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
AT91C_UDP_EPINT0 EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt
AT91C_UDP_EPINT1 EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt
AT91C_UDP_EPINT2 EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt
AT91C_UDP_EPINT3 EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt
AT91C_UDP_EPINT4 EQU (0x1:SHL:4) ;- (UDP) Endpoint 4 Interrupt
AT91C_UDP_EPINT5 EQU (0x1:SHL:5) ;- (UDP) Endpoint 5 Interrupt
AT91C_UDP_EPINT6 EQU (0x1:SHL:6) ;- (UDP) Endpoint 6 Interrupt
AT91C_UDP_EPINT7 EQU (0x1:SHL:7) ;- (UDP) Endpoint 7 Interrupt
AT91C_UDP_RXSUSP EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt
AT91C_UDP_RXRSM EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt
AT91C_UDP_EXTRSM EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt
AT91C_UDP_SOFINT EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt
AT91C_UDP_WAKEUP EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt
;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
AT91C_UDP_ENDBUSRES EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt
;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
AT91C_UDP_EP0 EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0
AT91C_UDP_EP1 EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1
AT91C_UDP_EP2 EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2
AT91C_UDP_EP3 EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3
AT91C_UDP_EP4 EQU (0x1:SHL:4) ;- (UDP) Reset Endpoint 4
AT91C_UDP_EP5 EQU (0x1:SHL:5) ;- (UDP) Reset Endpoint 5
AT91C_UDP_EP6 EQU (0x1:SHL:6) ;- (UDP) Reset Endpoint 6
AT91C_UDP_EP7 EQU (0x1:SHL:7) ;- (UDP) Reset Endpoint 7
;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
AT91C_UDP_TXCOMP EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR
AT91C_UDP_RX_DATA_BK0 EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0
AT91C_UDP_RXSETUP EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints)
AT91C_UDP_ISOERROR EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints)
AT91C_UDP_TXPKTRDY EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready
AT91C_UDP_FORCESTALL EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
AT91C_UDP_RX_DATA_BK1 EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
AT91C_UDP_DIR EQU (0x1:SHL:7) ;- (UDP) Transfer Direction
AT91C_UDP_EPTYPE EQU (0x7:SHL:8) ;- (UDP) Endpoint type
AT91C_UDP_EPTYPE_CTRL EQU (0x0:SHL:8) ;- (UDP) Control
AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1:SHL:8) ;- (UDP) Isochronous OUT
AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUT
AT91C_UDP_EPTYPE_INT_OUT EQU (0x3:SHL:8) ;- (UDP) Interrupt OUT
AT91C_UDP_EPTYPE_ISO_IN EQU (0x5:SHL:8) ;- (UDP) Isochronous IN
AT91C_UDP_EPTYPE_BULK_IN EQU (0x6:SHL:8) ;- (UDP) Bulk IN
AT91C_UDP_EPTYPE_INT_IN EQU (0x7:SHL:8) ;- (UDP) Interrupt IN
AT91C_UDP_DTGLE EQU (0x1:SHL:11) ;- (UDP) Data Toggle
AT91C_UDP_EPEDS EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable Disable
AT91C_UDP_RXBYTECNT EQU (0x7FF:SHL:16) ;- (UDP) Number Of Bytes Available in the FIFO
;- -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
AT91C_UDP_TXVDIS EQU (0x1:SHL:8) ;- (UDP)
AT91C_UDP_PUON EQU (0x1:SHL:9) ;- (UDP) Pull-up ON
;- *****************************************************************************
;- REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
;- *****************************************************************************
;- ========== Register definition for SYS peripheral ==========
;- ========== Register definition for AIC peripheral ==========
AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register
AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register
AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
;- ========== Register definition for PDC_DBGU peripheral ==========
AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
;- ========== Register definition for DBGU peripheral ==========
AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register
AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register
AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
;- ========== Register definition for PIOA peripheral ==========
AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register
AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register
AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register
AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
A