/***************************************************************************
**
** This file defines the special function registers for the
** Texas Instrument TMS470R1A128 device.
**
** Used with ICCARM and AARM.
**
** (c) Copyright IAR Systems 2004
**
** $Revision: 1.4 $
**
***************************************************************************/
#ifndef __IOTMS470R1A128_H
#define __IOTMS470R1A128_H
#if (((__TID__ >> 8) & 0x7F) != 0x4F) /* 0x4f = 79 dec */
#error This file should only be compiled by ICCARM/AARM
#endif
#include "io_macros.h"
/***************************************************************************
***************************************************************************
**
** IOTMS470R1A128 SPECIAL FUNCTION REGISTERS
**
***************************************************************************
***************************************************************************/
/* C specific declarations ************************************************/
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#if __LITTLE_ENDIAN__ == 1
#error This file should only be compiled in big endian mode
#endif
/* MPU control register */
typedef struct {
__REG32 CHAN0Special :1;
__REG32 CHAN0EN :1;
__REG32 CHAN0PRIV :1;
__REG32 CHAN0RONLY :1;
__REG32 CHAN1Special :1;
__REG32 CHAN1EN :1;
__REG32 CHAN1PRIV :1;
__REG32 CHAN1RONLY :1;
__REG32 CHAN2Special :1;
__REG32 CHAN2EN :1;
__REG32 CHAN2PRIV :1;
__REG32 CHAN2RONLY :1;
__REG32 CHAN3Special :1;
__REG32 CHAN3EN :1;
__REG32 CHAN3PRIV :1;
__REG32 CHAN3RONLY :1;
__REG32 :16;
} __mpuctrl_bits;
/* MPUAHR MPU Address High Register */
typedef struct {
__REG32 UPPERBOUND :16;
__REG32 :16;
} __mpuahr_bits;
/* MPUALR MPU Address Low Register */
typedef struct {
__REG32 LOWERBOUND :16;
__REG32 EQUAL :3;
__REG32 :13;
} __mpualr_bits;
/* Static memory control register 0 */
typedef struct {
__REG32 DW :2;
__REG32 :1;
__REG32 END :1;
__REG32 WS :4;
__REG32 :1;
__REG32 TWS :3;
__REG32 ASC :2;
__REG32 :18;
} __smcr0_bits;
/* Static memory control registers 1 - 9 */
typedef struct {
__REG32 DW :2;
__REG32 MLOC :1;
__REG32 END :1;
__REG32 WS :4;
__REG32 :1;
__REG32 TWS :3;
__REG32 ASC :2;
__REG32 :18;
} __smcrx_bits;
/* Write control register */
typedef struct {
__REG32 WBENABLE :1;
__REG32 WTWSOVR :1;
__REG32 :30;
} __wcr_bits;
/* Peripheral clock register */
typedef struct {
__REG32 PENABLE :1;
__REG32 CLKDIV :4;
__REG32 :27;
} __pcr_bits;
/* Peripheral location register */
typedef struct {
__REG32 PLOC0 :1;
__REG32 PLOC1 :1;
__REG32 PLOC2 :1;
__REG32 PLOC3 :1;
__REG32 PLOC4 :1;
__REG32 PLOC5 :1;
__REG32 PLOC6 :1;
__REG32 PLOC7 :1;
__REG32 PLOC8 :1;
__REG32 PLOC9 :1;
__REG32 PLOC10 :1;
__REG32 PLOC11 :1;
__REG32 PLOC12 :1;
__REG32 PLOC13 :1;
__REG32 PLOC14 :1;
__REG32 PLOC15 :1;
__REG32 :16;
} __plr_bits;
/* Peripheral protection register */
typedef struct {
__REG32 PPROT0 :1;
__REG32 PPROT1 :1;
__REG32 PPROT2 :1;
__REG32 PPROT3 :1;
__REG32 PPROT4 :1;
__REG32 PPROT5 :1;
__REG32 PPROT6 :1;
__REG32 PPROT7 :1;
__REG32 PPROT8 :1;
__REG32 PPROT9 :1;
__REG32 PPROT10 :1;
__REG32 PPROT11 :1;
__REG32 PPROT12 :1;
__REG32 PPROT13 :1;
__REG32 PPROT14 :1;
__REG32 PPROT15 :1;
__REG32 :16;
} __pprot_bits;
/* Memory Fine Base Address High Registers */
typedef struct {
__REG32 Address31_16 :16;
__REG32 :16;
} __mfbahr_bits;
/* Memory Fine Base Address Low Registers 0 */
typedef struct {
__REG32 PRIV :1;
__REG32 RONLY :1;
__REG32 :2;
__REG32 BlockSize :4;
__REG32 MS :1;
__REG32 :1;
__REG32 Address15_10 :6;
__REG32 :16;
} __mfbalr0_bits;
/* Memory Fine Base Address Low Registers 1 - 9 */
typedef struct {
__REG32 PRIV :1;
__REG32 RONLY :1;
__REG32 :2;
__REG32 BlockSize :4;
__REG32 :1;
__REG32 AW :1;
__REG32 Address15_10 :6;
__REG32 :16;
} __mfbalrx_bits;
/* Memory Coarse Base Address High Registers */
typedef struct {
__REG32 Address31_16 :16;
__REG32 :16;
} __mcbahr_bits;
/* Memory Coarse Base Address Low Registers */
typedef struct {
__REG32 PRIV :1;
__REG32 RONLY :1;
__REG32 :2;
__REG32 BlockSize :4;
__REG32 :1;
__REG32 AW :1;
__REG32 :5;
__REG32 Address15 :1;
__REG32 :16;
} __mcbalr_bits;
/* RTI Counter */
typedef struct {
__REG32 MOD10_0 :11;
__REG32 CNTR20_0 :21;
} __rticntr_bits;
/* RTI Preload Control Register */
typedef struct {
__REG32 PRELD10_0 :11;
__REG32 RTIM2_0 :3;
__REG32 :18;
} __rtipctl_bits;
/* RTI Control Register */
typedef struct {
__REG32 :6;
__REG32 TAPENA :1;
__REG32 TAPFLAG :1;
__REG32 :24;
} __rticntl_bits;
/* RTI Compare Register1 */
typedef struct {
__REG32 COMPARE1_20_0 :21;
__REG32 :11;
} __rticmp1_bits;
/* RTI Compare Register2 */
typedef struct {
__REG32 COMPARE2_20_0 :21;
__REG32 :11;
} __rticmp2_bits;
/* RTI Compare Interrupt Control Register */
typedef struct {
__REG32 :4;
__REG32 CMP2ENA :1;
__REG32 CMP1ENA :1;
__REG32 CMP2FLAG :1;
__REG32 CMP1FLAG :1;
__REG32 :24;
} __rticint_bits;
/* RTICNTEN RTI Count Enable Register */
typedef struct {
__REG32 CNTEN :2;
__REG32 :30;
} __rticnten_bits;
/* CLKCNTL Clock Control Register */
typedef struct {
__REG32 LPM :2;
__REG32 CLK_DIN :1;
__REG32 CLK_DOUT :1;
__REG32 CLK_DIR :1;
__REG32 CLKSR :2;
__REG32 PPW_NOVR :1;
__REG32 :24;
} __clkcntl_bits;
/* GCR Global Control Register (old name GLBCTRL) */
typedef struct {
__REG32 CLK_DIV_PRE :3;
__REG32 MULT4 :1;
__REG32 FLCONFIG :1;
__REG32 :9;
__REG32 RTI_CTRL :1;
__REG32 RST_OSC_FAIL_EN :1;
__REG32 :16;
} __gcr_bits;
/* SYSECR System Exception Control Register */
typedef struct {
__REG32 ILL_OVR :1;
__REG32 ACC_OVR :1;
__REG32 PACC_OVR :1;
__REG32 :11;
__REG32 RESET :2;
__REG32 :16;
} __sysecr_bits;
/* SYSESR System Reset Exception Status Register */
typedef struct {
__REG32 :7;
__REG32 SW_RST :1;
__REG32 ILL_MAP :1;
__REG32 PILL_ACC :1;
__REG32 ILL_ACC :1;
__REG32 ILL_ADR :1;
__REG32 ILL_MODE :1;
__REG32 WD_RST :1;
__REG32 CLK_RST :1;
__REG32 POR_RST :1;
__REG32 :16;
} __sysesr_bits;
/* ABRTESR Abort Exception Status Register */
typedef struct {
__REG32 :13;
__REG32 PACC_VIO :1;
__REG32 MEM_ABT :1;
__REG32 ADR_ABT :1;
__REG32 :16;
} __abrtesr_bits;
/* IRQIVEC IRQ Index Offset Vector Register */
typedef struct {
__REG32 IRQIVEC_7_0 :8;
__REG32 :24;
} __irqivec_bits;
/* FIQIVEC FIQ Index Offset Vector Registers */
typedef struct {
__REG32 FIQIVEC_7_0 :8;
__REG32 :24;
} __fiqivec_bits;
/* CIMIVEC CIM Index Offset Vector Register */
typedef struct {
__REG32 CIMIVEC_7_0 :8;
__REG32 :24;
} __cimivec_bits;
/* PSAENABLE PSA Enable */
typedef struct {
__REG32 PSADIS :1;
__REG32 :31;
} __psaenable_bits;
/* GLBSTAT Global Status Register */
typedef struct {
__REG32 PLL_SLIP :1;
__REG32 OSC_FAIL :1;
__REG32 :2;
__REG32 MPU_ACC :1;
__REG32 MPU_ADDR :1;
__REG32 SYS_ACC :1;
__REG32 SYS_ADDR :1;
__REG32 :24;
} __glbstat_bits;
/* DEV Device Identification Register */
typedef struct {
__REG32 DEV_15_0 :16;
__REG32 :16;
} __dev_bits;
/* SSIF System Software Interrupt Flag Register */
typedef struct {
__REG32 SSIF :1;
__REG32 :31;
} __ssif_bits;
/* SSIR System Software Interrupt Request Register */
typedef struct {
__REG32 SSDATA_7_0 :8;
__REG32 SSKEY_7_0 :8;
__REG32 :16;
} __ssir_bits;
/* HETGCR Global Configuration Register */
typedef struct {
__REG32 ON :1;
__REG32 IGNORE_SUSPEND :1;
__REG32 DEBUG_STATUS :1;
__REG32 :5;
__REG32 ACCESS64 :1;
__REG32 :7;
__REG32 CLK_MASTER :1;
__REG32 :7;
__REG32 POWER_DOWN :1;
__REG32 :7;
} __hetgcr_bits;
/* HETPFR Prescale Factor Register */
typedef struct {
__REG32 HRPRES_FACTOR :6;
__REG32 :2;
__REG32 LRPRES_FACTOR :3;
__REG32 :21;
} __hetpfr_bits;
/* HETADDR HET Current Address Register */
typedef struct {
__REG32 HETADDR :8;
__REG32 :24;
} __hetaddr_bits;
/* HETOFF Offset Level Register */
typedef struct {
__REG32 OFFSET :8;
__REG32 :24;
} __hetoff_bits;
/* HETEXC1 Exception Control Register 1 */
typedef struct {
__REG32 PRGM_OVRFL_PRY :1;
__REG32 APCNT_UNDRFL_PRY:1;
__REG32 APCNT_OVRFL_PRY :1;
__REG32 :5;
__REG32 PRGM_OVRFL_ENA :1;
__REG32 :7;
__REG32 APCNT_UNDRFL_ENA:1;
__REG32 :7;
__REG32 APCNT_OVRFL_ENA :1;
__REG32 :7;
} __hetexc1_bits;
/* HETEXC2 Exception Control Register 2 */
typedef struct {
__REG32 PRGM_OVRFL_FLG :1;
__REG32 APCNT_UNDRFL_FLG:1;
__REG32 APCNT_OVRFL_FLG :1;
__REG32 :29;
} __hetexc2_bits;
/* HETHRSH HR Share Control Register */
typedef struct {
__REG32 HR_SHARE_0_1 :1;
__REG32 HR_SHARE_2_3 :1;
__REG32 HR_SHARE_4_5 :1;
__REG32 HR_SHARE_6_7 :1;
__REG32 HR_SHARE_8_9 :1;
__REG32 HR_SHARE_10_11 :1;
__REG32 HR_SHARE_12_13 :1;
__REG32 HR_SHARE_14_15 :1;
__REG32 HR_SHARE_16_17 :1;
__REG32 HR_SHARE_18_19 :1;
__REG32 HR_SHARE_20_21 :1;
__REG32 HR_SHARE_22_23 :1;
__REG32 :20;
} __hethrsh_bits;
/* HETXOR HR XOR Control Register */
typedef struct {
__REG32 HR_XOR_SHARE_0_1 :1;
__REG32 HR_XOR_SHARE_2_3 :1;
__REG32 HR_XOR_SHARE_4_5 :1;
__REG32 HR_XOR_SHARE_6_7 :1;
__REG32 HR_XOR_SHARE_8_9 :1;
__REG32 HR_XOR_SHARE_10_11:1;
__REG32 HR_XOR_SHARE_12_13:1;
__REG32 HR_XOR_SHARE_14_15:1;
__REG32 HR_XOR_SHARE_16_17:1;
__REG32 HR_XOR_SHARE_18_19:1;
__REG32 HR_XOR_SHARE_20_21:1;
__REG32 HR_XOR_SHARE_22_23:1;
__REG32 :20;
} __hetxor_bits;
/* SPICTRL1 SPI Control Register 1 */
typedef struct {
__REG32 CHARLEN :5;
__REG32 PRESCALE :8;
__REG32 :19;
} __spictrl1_bits;
/* SPICTRL2 SPI Control Register 2 */
typedef struct {
__REG32 PHASE :1;
__REG32 POLARITY :1;
__REG32 PWRDN :1;
__REG32 MASTER :1;
__REG32 SPIEN :1;
__REG32 CLKMOD :1;
__REG32 :26;
} __spictrl2_bits;
/* SPICTRL3 SPI Control Register 3 */
typedef struct {
__REG32 RXINTFLAG :1;
__REG32 RXINTEN :1;
__REG32 RCVR_OVRN :1;
__REG32 OVRNINTEN :1;
__REG32 :1;
__REG32 ENABLE_HIGH_Z :1;
__REG32 :26;
} __spictrl3_bits;
/* SPIDAT1 SPI Shift Register 0 */
typedef struct {
__REG32 SPIDAT0 :16;
__REG32 :16;
} __spidat0_bits;
/* SPIDAT1 SPI Shift Register 1 */
typedef struct {
__REG32 SPIDAT1 :16;
__REG32 :16;
} __spidat1_bits;
/* SPIBUF SPI Buffer Register */
typedef struct {
__REG32 SPIBUF :16;
__REG32 RXINTFLAG_IMG :1;
__REG32 RCVR_OVRN_IMG :1;
__REG32 :14;
} __spibuf_bits;
/* SPIEMU SPI Emulation Register */
typedef struct {
__REG32 SPIEMU :16;
__REG32 :16;
} __spiemu_bits;
/* SPIPC1 SPI Pin Control Register 1 */
typedef struct {
__REG32 ENA_DIR :1;
__REG32 CLK_DIR :1;
__REG32 SIMO_DIR :1;
__REG32 SOMI_DIR :1;
__REG32 SCS_DIR :1;
__REG32 :27;
} __spipc1_bits;
/* SPIPC2 SPI Pin Control Register 2 */
typedef struct {
__REG32 ENA_DIN :1;
__REG32 CLK_DIN :1;
__REG32 SIMO_DIN :1;
__REG32 SOMI_DIN :1;
__REG32 SCS_DIN :1;
__REG32 :27;
} __spipc2_bits;
/* SPIPC3 SPI Pin Control Register 3 */
typedef struct {
__REG32 ENA_DOUT :1;
__REG32 CLK_DOUT :1;
__REG32 SIMO_DOUT :1;
__REG32 SOMI_DOUT :1;
__REG32 SCS_DOUT :1;
__REG32 :27;
} __spipc3_bits;
/* SPIPC4 SPI Pin Control Register 4 */
typedef struct {
__REG32 ENA_DSET :1;
__REG32 CLK_DSET :1;
__REG32 SIMO_DSET :1;
__REG32 SOMI_DSET :1;
__REG32 SCS_DSET :1;
__REG32 :27;
} __spipc4_bits;
/* SPIPC5 SPI Pin Control Register 5 */
typedef struct {
__REG32 ENA_DCLR :1;
__REG32 CLK_DCLR :1;
__REG32 SIMO_DCLR :1;
__REG32 SOMI_DCLR :1;
__REG32 SCS_DCLR :1;
__REG32 :27;
} __spipc5_bits;
/* SPIPC6 SPI Pin Control Register 6 */
typedef struct {
__REG32 ENA_FUN :1;
__REG32 CLK_FUN :1;
__REG32 SIMO_FUN :1;
__REG32 SOMI_FUN :1;
__REG32 SCS_FUN :1;
__REG32 :27;
} __spipc6_bits;
/* SCICCR Communication Control Register */
typedef struct {
__REG8 CHAR0 :1;
__REG8 CHAR1 :1;
__REG8 CHAR2 :1;
__REG8 COMM_MODE :1;
__REG8 TIMING_MODE :1;
__REG8 PARITY_ENA :1;
__REG8 PARITY :1;
__REG8 STOP :1;
} __sciccr_bits;
/* SCICTL1 SCI Control Register 1 */
typedef struct {
__REG8 RXENA :1;
__REG8 RXWAKE :1;
__REG8 RXRDY :1;
__REG8 SLEEP :1;
__REG8 IDLE :1;
__REG8 :3;
} __scictl1_bits;
/* SCICTL2 SCI Control Register 2 */
typedef struct {
__REG8 TXENA :1;
__REG8 TXWAKE :1;
__REG8 TXRDY :1;
__REG8 TX_EMPTY :1;
__REG8 :2;
__REG8 LOOP_BACK :1;
__REG8 CONT :1;
} __scictl2_bits;
/* SCICTL3 SCI Control Register 3 */
typedef struct {
__REG8 RXERR_INT_ENA :1;
__REG8 BRKDT_INT_ENA :1;
__REG8 WAKEUP_INT_ENA :1;
__REG8 TX_ACTION_ENA :1;
__REG8 RX_ACTION_ENA :1;
__REG8 CLOCK :1;
__REG8 POWER_DOWN :1;
__REG8 SW_RESET :1;
} __scictl3_bits;
/* SCIRXST Receiver Status Register */
typedef struct {
__REG8 RXERR :1;
__REG8 BRKDT :1;
__REG8 WAKEUP :1;
__REG8 PE :1;
__REG8 OE :1;
__REG8 FE :1;
__REG8 :1;
__REG8 BUS_BUSY :1;
} __scirxst_bits;
/* SCIPC1 Pin Control Register 1 */
typedef struct {
__REG8 CLK_DATA_DIR :1;
__REG8 CLK_FUNC :1;
__REG8 CLK_DATA_OUT :1;
__REG8 CLK_DATA_IN :1;
__REG8 :4;
} __scipc1_bits;
/* SCIPC2 Pin Control Register 2 */
typedef struct {
__REG8 RX_DATA_DIR :1;
__REG8 RX_FUNC :1;
__REG8 RX_DATA_OUT :1;
__REG8 RX_DATA_IN :1;
__REG8 :4;
} __scipc2_bits;
/* SCIPC3 Pin Control Register 2 */
typedef struct {
__REG8 TX_DATA_DIR :1;
__REG8 TX_FUNC :1;
__REG8 TX_DATA_OUT :1;
__REG8 TX_DATA_IN :1;
__REG8 :4;
} __scipc3_bits;
/* ADCR1 AD Control Register 1 */
typedef struct {
__REG16 PS :3;
__REG16 ACQ :2;
__REG16 ADC_EN :1;
__REG16 :2;
__REG16 PWR_DN :1;
__REG16 SELF_TST :1;
__REG16 HILO :1;
__REG16 BRIDGE_EN :1;
__REG16 CAL_ST :1;
__REG16 CAL_EN :1;
__REG16 :1;
__REG16 COS :1;
} __adccr1_bits;
/* ADCR2 AD Control Register 2 */
typedef struct {
__REG16 ENA_G2_INT :1;
__REG16 FRZ_G2 :1;
__REG16 G2_MODE :1;
__REG16 ENA_G1_INT :1;
__REG16 FRZ_G1 :1;
__REG16 G1_MODE :1;
__REG16 :2;
__REG16 EV_EDG_SEL :1;
__REG16 ENA_EV_INT :1;
__REG16 FRZ_EV :1;
__REG16 EV_MODE :1;
__REG16 :4;
} __adccr2_bits;
/* ADSR AD Status Register */
typedef struct {
__REG16 EV_END :1;
__REG16 G2_END :1;
__REG16 G1_END :1;
__REG16 :5;
__REG16 EV_STOP :1;
__REG16 G2_STOP :1;
__REG16 G1_STOP :1;
__REG16 EV_BUSY :1;
__REG16 G2_BUSY :1;
__REG16 G1_BUSY :1;
__REG16 :2;
} __adsr_bits;
/* ADCALR Calibration and Offset Error Correction Register */
typedef struct {
__REG16 CALR :10;
__REG16 :6;
} __adcalr_bits;
/* ADDR0 Digital Result Registers */
typedef struct {
__REG16 DT :10;
__REG16 :5;
__REG16 DT_ST :1;
} __addr_bits;
/* ADEMDR0 Emulation Digital Result Registers */
typedef struct {
__REG16 EDT_9_0 :10;
__REG16 :5;
__REG16 EDT_ST :1;
} __ademdr_bits;
typedef union {
/* ADEMDR0 Emulation Digital Result Registers */
struct {
__REG16 EDT_9_0 :10;
__REG16 :5;
__REG16 EDT_ST :1;
};
/* ADBUFE AD Event FIFO Buffer */
struct {
__REG16 EVDR :10;
__REG16 EVCHID :4;
__REG16 :1;
__REG16 EV_EMPTY :1;
};
} __ademdr014adbufe_bits;
typedef union{
/* Buffered mode */
/* ADEMDR4 Emulation Digital Result Registers */
struct {
__REG16 EDT_9_0 :10;
__REG16 &nb