/***************************************************************************
**
** This file defines the Special Function Registers for
** Texas Instruments TMS470R1A1M
**
** Used with ARM IAR C/C++ Compiler and Assembler.
**
** (c) Copyright IAR Systems 2005
**
** $Revision: 1.3 $
**
***************************************************************************/
#ifndef __IOTMS470R1A1M_H
#define __IOTMS470R1A1M_H
#if (((__TID__ >> 8) & 0x7F) != 0x4F) /* 0x4F = 79 dec */
#error This file should only be compiled by ARM IAR compiler and assembler
#endif
#include "io_macros.h"
/***************************************************************************
***************************************************************************
**
** TMS470R1A1M SPECIAL FUNCTION REGISTERS
**
***************************************************************************
***************************************************************************/
/* C-compiler specific declarations **********************************************/
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#if __LITTLE_ENDIAN__ == 1
#error This file should only be compiled in big endian mode
#endif
/* MPU - MPU control register */
typedef struct {
__REG32 CHAN0Special :1;
__REG32 CHAN0EN :1;
__REG32 CHAN0PRIV :1;
__REG32 CHAN0RONLY :1;
__REG32 CHAN1Special :1;
__REG32 CHAN1EN :1;
__REG32 CHAN1PRIV :1;
__REG32 CHAN1RONLY :1;
__REG32 CHAN2Special :1;
__REG32 CHAN2EN :1;
__REG32 CHAN2PRIV :1;
__REG32 CHAN2RONLY :1;
__REG32 CHAN3Special :1;
__REG32 CHAN3EN :1;
__REG32 CHAN3PRIV :1;
__REG32 CHAN3RONLY :1;
__REG32 :16;
} __mpuctrl_bits;
/* MPU - MPUAHR MPU Address High Register */
typedef struct {
__REG32 UPPERBOUND :16;
__REG32 :16;
} __mpuahr_bits;
/* MPU - MPUALR MPU Address Low Register */
typedef struct {
__REG32 LOWERBOUND :16;
__REG32 EQUAL :3;
__REG32 :13;
} __mpualr_bits;
/* SMC - Static memory control register 0 */
typedef struct {
__REG32 DW :2;
__REG32 :1;
__REG32 END :1;
__REG32 WS :4;
__REG32 :1;
__REG32 TWS :3;
__REG32 ASC :2;
__REG32 :18;
} __smcr0_bits;
/* SMC - Static memory control registers 1 - 9 */
typedef struct {
__REG32 DW :2;
__REG32 MLOC :1;
__REG32 END :1;
__REG32 WS :4;
__REG32 :1;
__REG32 TWS :3;
__REG32 ASC :2;
__REG32 :18;
} __smcrx_bits;
/* SMC - Write control register */
typedef struct {
__REG32 WBENABLE :1;
__REG32 WTWSOVR :1;
__REG32 :30;
} __wcr_bits;
/* SMC - Peripheral location register */
typedef struct {
__REG32 PLOC0 :1;
__REG32 PLOC1 :1;
__REG32 PLOC2 :1;
__REG32 PLOC3 :1;
__REG32 PLOC4 :1;
__REG32 PLOC5 :1;
__REG32 PLOC6 :1;
__REG32 PLOC7 :1;
__REG32 PLOC8 :1;
__REG32 PLOC9 :1;
__REG32 PLOC10 :1;
__REG32 PLOC11 :1;
__REG32 PLOC12 :1;
__REG32 PLOC13 :1;
__REG32 PLOC14 :1;
__REG32 PLOC15 :1;
__REG32 :16;
} __plr_bits;
/* SMC - Peripheral protection register */
typedef struct {
__REG32 PPROT0 :1;
__REG32 PPROT1 :1;
__REG32 PPROT2 :1;
__REG32 PPROT3 :1;
__REG32 PPROT4 :1;
__REG32 PPROT5 :1;
__REG32 PPROT6 :1;
__REG32 PPROT7 :1;
__REG32 PPROT8 :1;
__REG32 PPROT9 :1;
__REG32 PPROT10 :1;
__REG32 PPROT11 :1;
__REG32 PPROT12 :1;
__REG32 PPROT13 :1;
__REG32 PPROT14 :1;
__REG32 PPROT15 :1;
__REG32 :16;
} __pprot_bits;
/* SMC - Memory Fine Base Address High Registers */
typedef struct {
__REG32 Address31_16 :16;
__REG32 :16;
} __mfbahr_bits;
/* SMC - Memory Fine Base Address Low Registers 0 */
typedef struct {
__REG32 PRIV :1;
__REG32 RONLY :1;
__REG32 :2;
__REG32 BlockSize :4;
__REG32 MS :1;
__REG32 :1;
__REG32 Address15_10 :6;
__REG32 :16;
} __mfbalr0_bits;
/* SMC - Memory Fine Base Address Low Registers 1 - 9 */
typedef struct {
__REG32 PRIV :1;
__REG32 RONLY :1;
__REG32 :2;
__REG32 BlockSize :4;
__REG32 :1;
__REG32 AW :1;
__REG32 Address15_10 :6;
__REG32 :16;
} __mfbalrx_bits;
/* SMC - Memory Coarse Base Address High Registers */
typedef struct {
__REG32 Address31_16 :16;
__REG32 :16;
} __mcbahr_bits;
/* SMC - Memory Coarse Base Address Low Registers */
typedef struct {
__REG32 PRIV :1;
__REG32 RONLY :1;
__REG32 :2;
__REG32 BlockSize :4;
__REG32 :1;
__REG32 AW :1;
__REG32 :5;
__REG32 Address15 :1;
__REG32 :16;
} __mcbalr_bits;
/* SMC - RTI Counter */
typedef struct {
__REG32 MOD10_0 :11;
__REG32 CNTR20_0 :21;
} __rticntr_bits;
/* SMC - RTI Preload Control Register */
typedef struct {
__REG32 PRELD10_0 :11;
__REG32 RTIM2_0 :3;
__REG32 :18;
} __rtipctl_bits;
/* RTI Control Register */
typedef struct {
__REG32 :6;
__REG32 TAPENA :1;
__REG32 TAPFLAG :1;
__REG32 :24;
} __rticntl_bits;
/* RTI Compare Register1 */
typedef struct {
__REG32 COMPARE1_20_0 :21;
__REG32 :11;
} __rticmp1_bits;
/* SMC - RTI Compare Register2 */
typedef struct {
__REG32 COMPARE2_20_0 :21;
__REG32 :11;
} __rticmp2_bits;
/* SMC - RTI Compare Interrupt Control Register */
typedef struct {
__REG32 :4;
__REG32 CMP2ENA :1;
__REG32 CMP1ENA :1;
__REG32 CMP2FLAG :1;
__REG32 CMP1FLAG :1;
__REG32 :24;
} __rticint_bits;
/* SMC - RTICNTEN RTI Count Enable Register */
typedef struct {
__REG32 CNTEN :2;
__REG32 :30;
} __rticnten_bits;
/* SMC - IRQIVEC IRQ Index Offset Vector Register */
typedef struct {
__REG32 IRQIVEC_7_0 :8;
__REG32 :24;
} __irqivec_bits;
/* SMC - FIQIVEC FIQ Index Offset Vector Registers */
typedef struct {
__REG32 FIQIVEC_7_0 :8;
__REG32 :24;
} __fiqivec_bits;
/* SMC - CIMIVEC CIM Index Offset Vector Register */
typedef struct {
__REG32 CIMIVEC_7_0 :8;
__REG32 :24;
} __cimivec_bits;
/* SMC - SSIF System Software Interrupt Flag Register */
typedef struct {
__REG32 SSIF :1;
__REG32 :31;
} __ssif_bits;
/* SMC - SSIR System Software Interrupt Request Register */
typedef struct {
__REG32 SSDATA_7_0 :8;
__REG32 SSKEY_7_0 :8;
__REG32 :16;
} __ssir_bits;
/* SMC - PSAENABLE PSA Enable */
typedef struct {
__REG32 PSADIS :1;
__REG32 :31;
} __psaenable_bits;
/* SMC - Peripheral clock register */
typedef struct {
__REG32 PENABLE :1;
__REG32 CLKDIV :4;
__REG32 :27;
} __pcr_bits;
/* SMC - CLKCNTL Clock Control Register */
typedef struct {
__REG32 LPM :2;
__REG32 CLK_DIN :1;
__REG32 CLK_DOUT :1;
__REG32 CLK_DIR :1;
__REG32 CLKSR :2;
__REG32 PPW_NOVR :1;
__REG32 :24;
} __clkcntl_bits;
/* SMC - GCR Global Control Register (old name GLBCTRL) */
typedef struct {
__REG32 CLK_DIV_PRE :3;
__REG32 MULT4 :1;
__REG32 FLCONFIG :1;
__REG32 :9;
__REG32 RTI_CTRL :1;
__REG32 RST_OSC_FAIL_EN :1;
__REG32 :16;
} __gcr_bits;
/* SMC - SYSECR System Exception Control Register */
typedef struct {
__REG32 ILL_OVR :1;
__REG32 ACC_OVR :1;
__REG32 PACC_OVR :1;
__REG32 :11;
__REG32 RESET :2;
__REG32 :16;
} __sysecr_bits;
/* SMC - SYSESR System Reset Exception Status Register */
typedef struct {
__REG32 :7;
__REG32 SW_RST :1;
__REG32 ILL_MAP :1;
__REG32 PILL_ACC :1;
__REG32 ILL_ACC :1;
__REG32 ILL_ADR :1;
__REG32 ILL_MODE :1;
__REG32 WD_RST :1;
__REG32 CLK_RST :1;
__REG32 POR_RST :1;
__REG32 :16;
} __sysesr_bits;
/* SMC - ABRTESR Abort Exception Status Register */
typedef struct {
__REG32 :13;
__REG32 PACC_VIO :1;
__REG32 MEM_ABT :1;
__REG32 ADR_ABT :1;
__REG32 :16;
} __abrtesr_bits;
/* SMC - GLBSTAT Global Status Register */
typedef struct {
__REG32 PLL_SLIP :1;
__REG32 OSC_FAIL :1;
__REG32 :2;
__REG32 MPU_ACC :1;
__REG32 MPU_ADDR :1;
__REG32 SYS_ACC :1;
__REG32 SYS_ADDR :1;
__REG32 :24;
} __glbstat_bits;
/* SMC - DEV Device Identification Register */
typedef struct {
__REG32 DEV_15_0 :16;
__REG32 :16;
} __dev_bits;
/* IEM - Interrupt Pending Register 0 (INTPEND0) */
typedef struct {
__REG32 INTPEND0 : 1;
__REG32 INTPEND1 : 1;
__REG32 INTPEND2 : 1;
__REG32 INTPEND3 : 1;
__REG32 INTPEND4 : 1;
__REG32 INTPEND5 : 1;
__REG32 INTPEND6 : 1;
__REG32 INTPEND7 : 1;
__REG32 INTPEND8 : 1;
__REG32 INTPEND9 : 1;
__REG32 INTPEND10 : 1;
__REG32 INTPEND11 : 1;
__REG32 INTPEND12 : 1;
__REG32 INTPEND13 : 1;
__REG32 INTPEND14 : 1;
__REG32 INTPEND15 : 1;
__REG32 INTPEND16 : 1;
__REG32 INTPEND17 : 1;
__REG32 INTPEND18 : 1;
__REG32 INTPEND19 : 1;
__REG32 INTPEND20 : 1;
__REG32 INTPEND21 : 1;
__REG32 INTPEND22 : 1;
__REG32 INTPEND23 : 1;
__REG32 INTPEND24 : 1;
__REG32 INTPEND25 : 1;
__REG32 INTPEND26 : 1;
__REG32 INTPEND27 : 1;
__REG32 INTPEND28 : 1;
__REG32 INTPEND29 : 1;
__REG32 INTPEND30 : 1;
__REG32 INTPEND31 : 1;
} __intpend0_bits;
/* IEM - Interrupt Pending Register 1 (INTPEND1) */
typedef struct {
__REG32 INTPEND32 : 1;
__REG32 INTPEND33 : 1;
__REG32 INTPEND34 : 1;
__REG32 INTPEND35 : 1;
__REG32 INTPEND36 : 1;
__REG32 INTPEND37 : 1;
__REG32 INTPEND38 : 1;
__REG32 INTPEND39 : 1;
__REG32 INTPEND40 : 1;
__REG32 INTPEND41 : 1;
__REG32 INTPEND42 : 1;
__REG32 INTPEND43 : 1;
__REG32 INTPEND44 : 1;
__REG32 INTPEND45 : 1;
__REG32 INTPEND46 : 1;
__REG32 INTPEND47 : 1;
__REG32 INTPEND48 : 1;
__REG32 INTPEND49 : 1;
__REG32 INTPEND50 : 1;
__REG32 INTPEND51 : 1;
__REG32 INTPEND52 : 1;
__REG32 INTPEND53 : 1;
__REG32 INTPEND54 : 1;
__REG32 INTPEND55 : 1;
__REG32 INTPEND56 : 1;
__REG32 INTPEND57 : 1;
__REG32 INTPEND58 : 1;
__REG32 INTPEND59 : 1;
__REG32 INTPEND60 : 1;
__REG32 INTPEND61 : 1;
__REG32 INTPEND62 : 1;
__REG32 INTPEND63 : 1;
} __intpend1_bits;
/* IEM - Interrupt Control Register 0 (INTCTRL0) */
typedef struct {
__REG32 INTMAP3 : 5;
__REG32 : 3;
__REG32 INTMAP2 : 5;
__REG32 : 3;
__REG32 INTMAP1 : 5;
__REG32 : 3;
__REG32 INTMAP0 : 5;
__REG32 : 3;
} __intctrl0_bits;
/* IEM - Interrupt Control Register 1 (INTCTRL1) */
typedef struct {
__REG32 INTMAP7 : 5;
__REG32 : 3;
__REG32 INTMAP6 : 5;
__REG32 : 3;
__REG32 INTMAP5 : 5;
__REG32 : 3;
__REG32 INTMAP4 : 5;
__REG32 : 3;
} __intctrl1_bits;
/* IEM - Interrupt Control Register 2 (INTCTRL2) */
typedef struct {
__REG32 INTMAP11 : 5;
__REG32 : 3;
__REG32 INTMAP10 : 5;
__REG32 : 3;
__REG32 INTMAP9 : 5;
__REG32 : 3;
__REG32 INTMAP8 : 5;
__REG32 : 3;
} __intctrl2_bits;
/* IEM - Interrupt Control Register 3 (INTCTRL3) */
typedef struct {
__REG32 INTMAP15 : 5;
__REG32 : 3;
__REG32 INTMAP14 : 5;
__REG32 : 3;
__REG32 INTMAP13 : 5;
__REG32 : 3;
__REG32 INTMAP12 : 5;
__REG32 : 3;
} __intctrl3_bits;
/* IEM - Interrupt Control Register 4 (INTCTRL4) */
typedef struct {
__REG32 INTMAP19 : 5;
__REG32 : 3;
__REG32 INTMAP18 : 5;
__REG32 : 3;
__REG32 INTMAP17 : 5;
__REG32 : 3;
__REG32 INTMAP16 : 5;
__REG32 : 3;
} __intctrl4_bits;
/* IEM - Interrupt Control Register 5 (INTCTRL5) */
typedef struct {
__REG32 INTMAP23 : 5;
__REG32 : 3;
__REG32 INTMAP22 : 5;
__REG32 : 3;
__REG32 INTMAP21 : 5;
__REG32 : 3;
__REG32 INTMAP20 : 5;
__REG32 : 3;
} __intctrl5_bits;
/* IEM - Interrupt Control Register 6 (INTCTRL6) */
typedef struct {
__REG32 INTMAP27 : 5;
__REG32 : 3;
__REG32 INTMAP26 : 5;
__REG32 : 3;
__REG32 INTMAP25 : 5;
__REG32 : 3;
__REG32 INTMAP24 : 5;
__REG32 : 3;
} __intctrl6_bits;
/* IEM - Interrupt Control Register 7 (INTCTRL7) */
typedef struct {
__REG32 INTMAP31 : 5;
__REG32 : 3;
__REG32 INTMAP30 : 5;
__REG32 : 3;
__REG32 INTMAP29 : 5;
__REG32 : 3;
__REG32 INTMAP28 : 5;
__REG32 : 3;
} __intctrl7_bits;
/* IEM - Interrupt Control Register 8 (INTCTRL8) */
typedef struct {
__REG32 INTMAP35 : 5;
__REG32 : 3;
__REG32 INTMAP34 : 5;
__REG32 : 3;
__REG32 INTMAP33 : 5;
__REG32 : 3;
__REG32 INTMAP32 : 5;
__REG32 : 3;
} __intctrl8_bits;
/* IEM - Interrupt Control Register 9 (INTCTRL9) */
typedef struct {
__REG32 INTMAP39 : 5;
__REG32 : 3;
__REG32 INTMAP38 : 5;
__REG32 : 3;
__REG32 INTMAP37 : 5;
__REG32 : 3;
__REG32 INTMAP36 : 5;
__REG32 : 3;
} __intctrl9_bits;
/* IEM - Interrupt Control Register 10 (INTCTRL10) */
typedef struct {
__REG32 INTMAP43 : 5;
__REG32 : 3;
__REG32 INTMAP42 : 5;
__REG32 : 3;
__REG32 INTMAP41 : 5;
__REG32 : 3;
__REG32 INTMAP40 : 5;
__REG32 : 3;
} __intctrl10_bits;
/* IEM - Interrupt Control Register 11 (INTCTRL11) */
typedef struct {
__REG32 INTMAP47 : 5;
__REG32 : 3;
__REG32 INTMAP46 : 5;
__REG32 : 3;
__REG32 INTMAP45 : 5;
__REG32 : 3;
__REG32 INTMAP44 : 5;
__REG32 : 3;
} __intctrl11_bits;
/* IEM - Interrupt Control Register 12 (INTCTRL12) */
typedef struct {
__REG32 INTMAP51 : 5;
__REG32 : 3;
__REG32 INTMAP50 : 5;
__REG32 : 3;
__REG32 INTMAP49 : 5;
__REG32 : 3;
__REG32 INTMAP48 : 5;
__REG32 : 3;
} __intctrl12_bits;
/* IEM - Interrupt Control Register 13 (INTCTRL13) */
typedef struct {
__REG32 INTMAP55 : 5;
__REG32 : 3;
__REG32 INTMAP54 : 5;
__REG32 : 3;
__REG32 INTMAP53 : 5;
__REG32 : 3;
__REG32 INTMAP52 : 5;
__REG32 : 3;
} __intctrl13_bits;
/* IEM - Interrupt Control Register 14 (INTCTRL14) */
typedef struct {
__REG32 INTMAP59 : 5;
__REG32 : 3;
__REG32 INTMAP58 : 5;
__REG32 : 3;
__REG32 INTMAP57 : 5;
__REG32 : 3;
__REG32 INTMAP56 : 5;
__REG32 : 3;
} __intctrl14_bits;
/* IEM - Interrupt Control Register 15 (INTCTRL15) */
typedef struct {
__REG32 INTMAP63 : 5;
__REG32 : 3;
__REG32 INTMAP62 : 5;
__REG32 : 3;
__REG32 INTMAP61 : 5;
__REG32 : 3;
__REG32 INTMAP60 : 5;
__REG32 : 3;
} __intctrl15_bits;
/* MSM - Status and Control Register (MSMSCR) */
typedef struct {
__REG32 SEC : 1;
__REG32 :30;
__REG32 FORCESEC : 1;
} __msmscr_bits;
/* HET - HETGCR Global Configuration Register */
typedef struct {
__REG32 ON :1;
__REG32 IGNORE_SUSPEND :1;
__REG32 DEBUG_STATUS :1;
__REG32 :5;
__REG32 ACCESS64 :1;
__REG32 :7;
__REG32 CLK_MASTER :1;
__REG32 :7;
__REG32 POWER_DOWN :1;
__REG32 :7;
} __hetgcr_bits;
/* HET - HETPFR Prescale Factor Register */
typedef struct {
__REG32 HRPRES_FACTOR :6;
__REG32 :2;
__REG32 LRPRES_FACTOR :3;
__REG32 :21;
} __hetpfr_bits;
/* HET - HETADDR HET Current Address Register */
typedef struct {
__REG32 HETADDR :8;
__REG32 :24;
} __hetaddr_bits;
/* HET - HETOFF Offset Level Register */
typedef struct {
__REG32 OFFSET :8;
__REG32 :24;
} __hetoff_bits;
/* HET - HETEXC1 Exception Control Register 1 */
typedef struct {
__REG32 PRGM_OVRFL_PRY :1;
__REG32 APCNT_UNDRFL_PRY:1;
__REG32 APCNT_OVRFL_PRY :1;
__REG32 :5;
__REG32 PRGM_OVRFL_ENA :1;
__REG32 :7;
__REG32 APCNT_UNDRFL_ENA:1;
__REG32 :7;
__REG32 APCNT_OVRFL_ENA :1;
__REG32 :7;
} __hetexc1_bits;
/* HET - HETEXC2 Exception Control Register 2 */
typedef struct {
__REG32 PRGM_OVRFL_FLG :1;
__REG32 APCNT_UNDRFL_FLG:1;
__REG32 APCNT_OVRFL_FLG :1;
__REG32 :29;
} __hetexc2_bits;
/* HET - HETHRSH HR Share Control Register */
typedef struct {
__REG32 HR_SHARE_0_1 :1;
__REG32 HR_SHARE_2_3 :1;
__REG32 HR_SHARE_4_5 :1;
__REG32 HR_SHARE_6_7 :1;
__REG32 HR_SHARE_8_9 :1;
__REG32 HR_SHARE_10_11 :1;
__REG32 HR_SHARE_12_13 :1;
__REG32 HR_SHARE_14_15 :1;
__REG32 HR_SHARE_16_17 :1;
__REG32 HR_SHARE_18_19 :1;
__REG32 HR_SHARE_20_21 :1;
__REG32 HR_SHARE_22_23 :1;
__REG32 :20;
} __hethrsh_bits;
/* HET - HETXOR HR XOR Control Register */
typedef struct {
__REG32 HR_XOR_SHARE_0_1 :1;
__REG32 HR_XOR_SHARE_2_3 :1;
__REG32 HR_XOR_SHARE_4_5 :1;
__REG32 HR_XOR_SHARE_6_7 :1;
__REG32 HR_XOR_SHARE_8_9 :1;
__REG32 HR_XOR_SHARE_10_11:1;
__REG32 HR_XOR_SHARE_12_13:1;
__REG32 HR_XOR_SHARE_14_15:1;
__REG32 HR_XOR_SHARE_16_17:1;
__REG32 HR_XOR_SHARE_18_19:1;
__REG32 HR_XOR_SHARE_20_21:1;
__REG32 HR_XOR_SHARE_22_23:1;
__REG32 :20;
} __hetxor_bits;
/* SPI - SPICTRL1 SPI Control Register 1 */
typedef struct {
__REG32 CHARLEN :5;
__REG32 PRESCALE :8;
__REG32 :19;
} __spictrl1_bits;
/* SPI - SPICTRL2 SPI Control Register 2 */
typedef struct {
__REG32 PHASE :1;
__REG32 POLARITY :1;
__REG32 PWRDN :1;
__REG32 MASTER :1;
__REG32 SPIEN :1;
__REG32 CLKMOD :1;
__REG32 :26;
}