/***************************************************************************
**
** This file defines the Special Function Registers for
** Texas Instruments TMS470R1A1M
**
** Used with ARM IAR C/C++ Compiler and Assembler.
**
** (c) Copyright IAR Systems 2005
**
** $Revision: 1.3 $
**
***************************************************************************/
#ifndef __IOTMS470R1A1M_H
#define __IOTMS470R1A1M_H
#if (((__TID__ >> 8) & 0x7F) != 0x4F) /* 0x4F = 79 dec */
#error This file should only be compiled by ARM IAR compiler and assembler
#endif
#include "io_macros.h"
/***************************************************************************
***************************************************************************
**
** TMS470R1A1M SPECIAL FUNCTION REGISTERS
**
***************************************************************************
***************************************************************************/
/* C-compiler specific declarations **********************************************/
#ifdef __IAR_SYSTEMS_ICC__
#ifndef _SYSTEM_BUILD
#pragma system_include
#endif
#if __LITTLE_ENDIAN__ == 1
#error This file should only be compiled in big endian mode
#endif
/* MPU - MPU control register */
typedef struct {
__REG32 CHAN0Special :1;
__REG32 CHAN0EN :1;
__REG32 CHAN0PRIV :1;
__REG32 CHAN0RONLY :1;
__REG32 CHAN1Special :1;
__REG32 CHAN1EN :1;
__REG32 CHAN1PRIV :1;
__REG32 CHAN1RONLY :1;
__REG32 CHAN2Special :1;
__REG32 CHAN2EN :1;
__REG32 CHAN2PRIV :1;
__REG32 CHAN2RONLY :1;
__REG32 CHAN3Special :1;
__REG32 CHAN3EN :1;
__REG32 CHAN3PRIV :1;
__REG32 CHAN3RONLY :1;
__REG32 :16;
} __mpuctrl_bits;
/* MPU - MPUAHR MPU Address High Register */
typedef struct {
__REG32 UPPERBOUND :16;
__REG32 :16;
} __mpuahr_bits;
/* MPU - MPUALR MPU Address Low Register */
typedef struct {
__REG32 LOWERBOUND :16;
__REG32 EQUAL :3;
__REG32 :13;
} __mpualr_bits;
/* SMC - Static memory control register 0 */
typedef struct {
__REG32 DW :2;
__REG32 :1;
__REG32 END :1;
__REG32 WS :4;
__REG32 :1;
__REG32 TWS :3;
__REG32 ASC :2;
__REG32 :18;
} __smcr0_bits;
/* SMC - Static memory control registers 1 - 9 */
typedef struct {
__REG32 DW :2;
__REG32 MLOC :1;
__REG32 END :1;
__REG32 WS :4;
__REG32 :1;
__REG32 TWS :3;
__REG32 ASC :2;
__REG32 :18;
} __smcrx_bits;
/* SMC - Write control register */
typedef struct {
__REG32 WBENABLE :1;
__REG32 WTWSOVR :1;
__REG32 :30;
} __wcr_bits;
/* SMC - Peripheral location register */
typedef struct {
__REG32 PLOC0 :1;
__REG32 PLOC1 :1;
__REG32 PLOC2 :1;
__REG32 PLOC3 :1;
__REG32 PLOC4 :1;
__REG32 PLOC5 :1;
__REG32 PLOC6 :1;
__REG32 PLOC7 :1;
__REG32 PLOC8 :1;
__REG32 PLOC9 :1;
__REG32 PLOC10 :1;
__REG32 PLOC11 :1;
__REG32 PLOC12 :1;
__REG32 PLOC13 :1;
__REG32 PLOC14 :1;
__REG32 PLOC15 :1;
__REG32 :16;
} __plr_bits;
/* SMC - Peripheral protection register */
typedef struct {
__REG32 PPROT0 :1;
__REG32 PPROT1 :1;
__REG32 PPROT2 :1;
__REG32 PPROT3 :1;
__REG32 PPROT4 :1;
__REG32 PPROT5 :1;
__REG32 PPROT6 :1;
__REG32 PPROT7 :1;
__REG32 PPROT8 :1;
__REG32 PPROT9 :1;
__REG32 PPROT10 :1;
__REG32 PPROT11 :1;
__REG32 PPROT12 :1;
__REG32 PPROT13 :1;
__REG32 PPROT14 :1;
__REG32 PPROT15 :1;
__REG32 :16;
} __pprot_bits;
/* SMC - Memory Fine Base Address High Registers */
typedef struct {
__REG32 Address31_16 :16;
__REG32 :16;
} __mfbahr_bits;
/* SMC - Memory Fine Base Address Low Registers 0 */
typedef struct {
__REG32 PRIV :1;
__REG32 RONLY :1;
__REG32 :2;
__REG32 BlockSize :4;
__REG32 MS :1;
__REG32 :1;
__REG32 Address15_10 :6;
__REG32 :16;
} __mfbalr0_bits;
/* SMC - Memory Fine Base Address Low Registers 1 - 9 */
typedef struct {
__REG32 PRIV :1;
__REG32 RONLY :1;
__REG32 :2;
__REG32 BlockSize :4;
__REG32 :1;
__REG32 AW :1;
__REG32 Address15_10 :6;
__REG32 :16;
} __mfbalrx_bits;
/* SMC - Memory Coarse Base Address High Registers */
typedef struct {
__REG32 Address31_16 :16;
__REG32 :16;
} __mcbahr_bits;
/* SMC - Memory Coarse Base Address Low Registers */
typedef struct {
__REG32 PRIV :1;
__REG32 RONLY :1;
__REG32 :2;
__REG32 BlockSize :4;
__REG32 :1;
__REG32 AW :1;
__REG32 :5;
__REG32 Address15 :1;
__REG32 :16;
} __mcbalr_bits;
/* SMC - RTI Counter */
typedef struct {
__REG32 MOD10_0 :11;
__REG32 CNTR20_0 :21;
} __rticntr_bits;
/* SMC - RTI Preload Control Register */
typedef struct {
__REG32 PRELD10_0 :11;
__REG32 RTIM2_0 :3;
__REG32 :18;
} __rtipctl_bits;
/* RTI Control Register */
typedef struct {
__REG32 :6;
__REG32 TAPENA :1;
__REG32 TAPFLAG :1;
__REG32 :24;
} __rticntl_bits;
/* RTI Compare Register1 */
typedef struct {
__REG32 COMPARE1_20_0 :21;
__REG32 :11;
} __rticmp1_bits;
/* SMC - RTI Compare Register2 */
typedef struct {
__REG32 COMPARE2_20_0 :21;
__REG32 :11;
} __rticmp2_bits;
/* SMC - RTI Compare Interrupt Control Register */
typedef struct {
__REG32 :4;
__REG32 CMP2ENA :1;
__REG32 CMP1ENA :1;
__REG32 CMP2FLAG :1;
__REG32 CMP1FLAG :1;
__REG32 :24;
} __rticint_bits;
/* SMC - RTICNTEN RTI Count Enable Register */
typedef struct {
__REG32 CNTEN :2;
__REG32 :30;
} __rticnten_bits;
/* SMC - IRQIVEC IRQ Index Offset Vector Register */
typedef struct {
__REG32 IRQIVEC_7_0 :8;
__REG32 :24;
} __irqivec_bits;
/* SMC - FIQIVEC FIQ Index Offset Vector Registers */
typedef struct {
__REG32 FIQIVEC_7_0 :8;
__REG32 :24;
} __fiqivec_bits;
/* SMC - CIMIVEC CIM Index Offset Vector Register */
typedef struct {
__REG32 CIMIVEC_7_0 :8;
__REG32 :24;
} __cimivec_bits;
/* SMC - SSIF System Software Interrupt Flag Register */
typedef struct {
__REG32 SSIF :1;
__REG32 :31;
} __ssif_bits;
/* SMC - SSIR System Software Interrupt Request Register */
typedef struct {
__REG32 SSDATA_7_0 :8;
__REG32 SSKEY_7_0 :8;
__REG32 :16;
} __ssir_bits;
/* SMC - PSAENABLE PSA Enable */
typedef struct {
__REG32 PSADIS :1;
__REG32 :31;
} __psaenable_bits;
/* SMC - Peripheral clock register */
typedef struct {
__REG32 PENABLE :1;
__REG32 CLKDIV :4;
__REG32 :27;
} __pcr_bits;
/* SMC - CLKCNTL Clock Control Register */
typedef struct {
__REG32 LPM :2;
__REG32 CLK_DIN :1;
__REG32 CLK_DOUT :1;
__REG32 CLK_DIR :1;
__REG32 CLKSR :2;
__REG32 PPW_NOVR :1;
__REG32 :24;
} __clkcntl_bits;
/* SMC - GCR Global Control Register (old name GLBCTRL) */
typedef struct {
__REG32 CLK_DIV_PRE :3;
__REG32 MULT4 :1;
__REG32 FLCONFIG :1;
__REG32 :9;
__REG32 RTI_CTRL :1;
__REG32 RST_OSC_FAIL_EN :1;
__REG32 :16;
} __gcr_bits;
/* SMC - SYSECR System Exception Control Register */
typedef struct {
__REG32 ILL_OVR :1;
__REG32 ACC_OVR :1;
__REG32 PACC_OVR :1;
__REG32 :11;
__REG32 RESET :2;
__REG32 :16;
} __sysecr_bits;
/* SMC - SYSESR System Reset Exception Status Register */
typedef struct {
__REG32 :7;
__REG32 SW_RST :1;
__REG32 ILL_MAP :1;
__REG32 PILL_ACC :1;
__REG32 ILL_ACC :1;
__REG32 ILL_ADR :1;
__REG32 ILL_MODE :1;
__REG32 WD_RST :1;
__REG32 CLK_RST :1;
__REG32 POR_RST :1;
__REG32 :16;
} __sysesr_bits;
/* SMC - ABRTESR Abort Exception Status Register */
typedef struct {
__REG32 :13;
__REG32 PACC_VIO :1;
__REG32 MEM_ABT :1;
__REG32 ADR_ABT :1;
__REG32 :16;
} __abrtesr_bits;
/* SMC - GLBSTAT Global Status Register */
typedef struct {
__REG32 PLL_SLIP :1;
__REG32 OSC_FAIL :1;
__REG32 :2;
__REG32 MPU_ACC :1;
__REG32 MPU_ADDR :1;
__REG32 SYS_ACC :1;
__REG32 SYS_ADDR :1;
__REG32 :24;
} __glbstat_bits;
/* SMC - DEV Device Identification Register */
typedef struct {
__REG32 DEV_15_0 :16;
__REG32 :16;
} __dev_bits;
/* IEM - Interrupt Pending Register 0 (INTPEND0) */
typedef struct {
__REG32 INTPEND0 : 1;
__REG32 INTPEND1 : 1;
__REG32 INTPEND2 : 1;
__REG32 INTPEND3 : 1;
__REG32 INTPEND4 : 1;
__REG32 INTPEND5 : 1;
__REG32 INTPEND6 : 1;
__REG32 INTPEND7 : 1;
__REG32 INTPEND8 : 1;
__REG32 INTPEND9 : 1;
__REG32 INTPEND10 : 1;
__REG32 INTPEND11 : 1;
__REG32 INTPEND12 : 1;
__REG32 INTPEND13 : 1;
__REG32 INTPEND14 : 1;
__REG32 INTPEND15 : 1;
__REG32 INTPEND16 : 1;
__REG32 INTPEND17 : 1;
__REG32 INTPEND18 : 1;
__REG32 INTPEND19 : 1;
__REG32 INTPEND20 : 1;
__REG32 INTPEND21 : 1;
__REG32 INTPEND22 : 1;
__REG32 INTPEND23 : 1;
__REG32 INTPEND24 : 1;
__REG32 INTPEND25 : 1;
__REG32 INTPEND26 : 1;
__REG32 INTPEND27 : 1;
__REG32 INTPEND28 : 1;
__REG32 INTPEND29 : 1;
__REG32 INTPEND30 : 1;
__REG32 INTPEND31 : 1;
} __intpend0_bits;
/* IEM - Interrupt Pending Register 1 (INTPEND1) */
typedef struct {
__REG32 INTPEND32 : 1;
__REG32 INTPEND33 : 1;
__REG32 INTPEND34 : 1;
__REG32 INTPEND35 : 1;
__REG32 INTPEND36 : 1;
__REG32 INTPEND37 : 1;
__REG32 INTPEND38 : 1;
__REG32 INTPEND39 : 1;
__REG32 INTPEND40 : 1;
__REG32 INTPEND41 : 1;
__REG32 INTPEND42 : 1;
__REG32 INTPEND43 : 1;
__REG32 INTPEND44 : 1;
__REG32 INTPEND45 : 1;
__REG32 INTPEND46 : 1;
__REG32 INTPEND47 : 1;
__REG32 INTPEND48 : 1;
__REG32 INTPEND49 : 1;
__REG32 INTPEND50 : 1;
__REG32 INTPEND51 : 1;
__REG32 INTPEND52 : 1;
__REG32 INTPEND53 : 1;
__REG32 INTPEND54 : 1;
__REG32 INTPEND55 : 1;
__REG32 INTPEND56 : 1;
__REG32 INTPEND57 : 1;
__REG32 INTPEND58 : 1;
__REG32 INTPEND59 : 1;
__REG32 INTPEND60 : 1;
__REG32 INTPEND61 : 1;
__REG32 INTPEND62 : 1;
__REG32 INTPEND63 : 1;
} __intpend1_bits;
/* IEM - Interrupt Control Register 0 (INTCTRL0) */
typedef struct {
__REG32 INTMAP3 : 5;
__REG32 : 3;
__REG32 INTMAP2 : 5;
__REG32 : 3;
__REG32 INTMAP1 : 5;
__REG32 : 3;
__REG32 INTMAP0 : 5;
__REG32 : 3;
} __intctrl0_bits;
/* IEM - Interrupt Control Register 1 (INTCTRL1) */
typedef struct {
__REG32 INTMAP7 : 5;
__REG32 : 3;
__REG32 INTMAP6 : 5;
__REG32 : 3;
__REG32 INTMAP5 : 5;
__REG32 : 3;
__REG32 INTMAP4 : 5;
__REG32 : 3;
} __intctrl1_bits;
/* IEM - Interrupt Control Register 2 (INTCTRL2) */
typedef struct {
__REG32 INTMAP11 : 5;
__REG32 : 3;
__REG32 INTMAP10 : 5;
__REG32 : 3;
__REG32 INTMAP9 : 5;
__REG32 : 3;
__REG32 INTMAP8 : 5;
__REG32 : 3;
} __intctrl2_bits;
/* IEM - Interrupt Control Register 3 (INTCTRL3) */
typedef struct {
__REG32 INTMAP15 : 5;
__REG32 : 3;
__REG32 INTMAP14 : 5;
__REG32 : 3;
__REG32 INTMAP13 : 5;
__REG32 : 3;
__REG32 INTMAP12 : 5;
__REG32 : 3;
} __intctrl3_bits;
/* IEM - Interrupt Control Register 4 (INTCTRL4) */
typedef struct {
__REG32 INTMAP19 : 5;
__REG32 : 3;
__REG32 INTMAP18 : 5;
__REG32 : 3;
__REG32 INTMAP17 : 5;
__REG32 : 3;
__REG32 INTMAP16 : 5;
__REG32 : 3;
} __intctrl4_bits;
/* IEM - Interrupt Control Register 5 (INTCTRL5) */
typedef struct {
__REG32 INTMAP23 : 5;
__REG32 : 3;
__REG32 INTMAP22 : 5;
__REG32 : 3;
__REG32 INTMAP21 : 5;
__REG32 : 3;
__REG32 INTMAP20 : 5;
__REG32 : 3;
} __intctrl5_bits;
/* IEM - Interrupt Control Register 6 (INTCTRL6) */
typedef struct {
__REG32 INTMAP27 : 5;
__REG32 : 3;
__REG32 INTMAP26 : 5;
__REG32 : 3;
__REG32 INTMAP25 : 5;
__REG32 : 3;
__REG32 INTMAP24 : 5;
__REG32 : 3;
} __intctrl6_bits;
/* IEM - Interrupt Control Register 7 (INTCTRL7) */
typedef struct {
__REG32 INTMAP31 : 5;
__REG32 : 3;
__REG32 INTMAP30 : 5;
__REG32 : 3;
__REG32 INTMAP29 : 5;
__REG32 : 3;
__REG32 INTMAP28 : 5;
__REG32 : 3;
} __intctrl7_bits;
/* IEM - Interrupt Control Register 8 (INTCTRL8) */
typedef struct {
__REG32 INTMAP35 : 5;
__REG32 : 3;
__REG32 INTMAP34 : 5;
__REG32 : 3;
__REG32 INTMAP33 : 5;
__REG32 : 3;
__REG32 INTMAP32 : 5;
__REG32 : 3;
} __intctrl8_bits;
/* IEM - Interrupt Control Register 9 (INTCTRL9) */
typedef struct {
__REG32 INTMAP39 : 5;
__REG32 : 3;
__REG32 INTMAP38 : 5;
__REG32 : 3;
__REG32 INTMAP37 : 5;
__REG32 : 3;
__REG32 INTMAP36 : 5;
__REG32 : 3;
} __intctrl9_bits;
/* IEM - Interrupt Control Register 10 (INTCTRL10) */
typedef struct {
__REG32 INTMAP43 : 5;
__REG32 : 3;
__REG32 INTMAP42 : 5;
__REG32 : 3;
__REG32 INTMAP41 : 5;
__REG32 : 3;
__REG32 INTMAP40 : 5;
__REG32 : 3;
} __intctrl10_bits;
/* IEM - Interrupt Control Register 11 (INTCTRL11) */
typedef struct {
__REG32 INTMAP47 : 5;
__REG32 : 3;
__REG32 INTMAP46 : 5;
__REG32 : 3;
__REG32 INTMAP45 : 5;
__REG32 : 3;
__REG32 INTMAP44 : 5;
__REG32 : 3;
} __intctrl11_bits;
/* IEM - Interrupt Control Register 12 (INTCTRL12) */
typedef struct {
__REG32 INTMAP51 : 5;
__REG32 : 3;
__REG32 INTMAP50 : 5;
__REG32 : 3;
__REG32 INTMAP49 : 5;
__REG32 : 3;
__REG32 INTMAP48 : 5;
__REG32 : 3;
} __intctrl12_bits;
/* IEM - Interrupt Control Register 13 (INTCTRL13) */
typedef struct {
__REG32 INTMAP55 : 5;
__REG32 : 3;
__REG32 INTMAP54 : 5;
__REG32 : 3;
__REG32 INTMAP53 : 5;
__REG32 : 3;
__REG32 INTMAP52 : 5;
__REG32 : 3;
} __intctrl13_bits;
/* IEM - Interrupt Control Register 14 (INTCTRL14) */
typedef struct {
__REG32 INTMAP59 : 5;
__REG32 : 3;
__REG32 INTMAP58 : 5;
__REG32 : 3;
__REG32 INTMAP57 : 5;
__REG32 : 3;
__REG32 INTMAP56 : 5;
__REG32 : 3;
} __intctrl14_bits;
/* IEM - Interrupt Control Register 15 (INTCTRL15) */
typedef struct {
__REG32 INTMAP63 : 5;
__REG32 : 3;
__REG32 INTMAP62 : 5;
__REG32 : 3;
__REG32 INTMAP61 : 5;
__REG32 : 3;
__REG32 INTMAP60 : 5;
__REG32 : 3;
} __intctrl15_bits;
/* MSM - Status and Control Register (MSMSCR) */
typedef struct {
__REG32 SEC : 1;
__REG32 :30;
__REG32 FORCESEC : 1;
} __msmscr_bits;
/* HET - HETGCR Global Configuration Register */
typedef struct {
__REG32 ON :1;
__REG32 IGNORE_SUSPEND :1;
__REG32 DEBUG_STATUS :1;
__REG32 :5;
__REG32 ACCESS64 :1;
__REG32 :7;
__REG32 CLK_MASTER :1;
__REG32 :7;
__REG32 POWER_DOWN :1;
__REG32 :7;
} __hetgcr_bits;
/* HET - HETPFR Prescale Factor Register */
typedef struct {
__REG32 HRPRES_FACTOR :6;
__REG32 :2;
__REG32 LRPRES_FACTOR :3;
__REG32 :21;
} __hetpfr_bits;
/* HET - HETADDR HET Current Address Register */
typedef struct {
__REG32 HETADDR :8;
__REG32 :24;
} __hetaddr_bits;
/* HET - HETOFF Offset Level Register */
typedef struct {
__REG32 OFFSET :8;
__REG32 :24;
} __hetoff_bits;
/* HET - HETEXC1 Exception Control Register 1 */
typedef struct {
__REG32 PRGM_OVRFL_PRY :1;
__REG32 APCNT_UNDRFL_PRY:1;
__REG32 APCNT_OVRFL_PRY :1;
__REG32 :5;
__REG32 PRGM_OVRFL_ENA :1;
__REG32 :7;
__REG32 APCNT_UNDRFL_ENA:1;
__REG32 :7;
__REG32 APCNT_OVRFL_ENA :1;
__REG32 :7;
} __hetexc1_bits;
/* HET - HETEXC2 Exception Control Register 2 */
typedef struct {
__REG32 PRGM_OVRFL_FLG :1;
__REG32 APCNT_UNDRFL_FLG:1;
__REG32 APCNT_OVRFL_FLG :1;
__REG32 :29;
} __hetexc2_bits;
/* HET - HETHRSH HR Share Control Register */
typedef struct {
__REG32 HR_SHARE_0_1 :1;
__REG32 HR_SHARE_2_3 :1;
__REG32 HR_SHARE_4_5 :1;
__REG32 HR_SHARE_6_7 :1;
__REG32 HR_SHARE_8_9 :1;
__REG32 HR_SHARE_10_11 :1;
__REG32 HR_SHARE_12_13 :1;
__REG32 HR_SHARE_14_15 :1;
__REG32 HR_SHARE_16_17 :1;
__REG32 HR_SHARE_18_19 :1;
__REG32 HR_SHARE_20_21 :1;
__REG32 HR_SHARE_22_23 :1;
__REG32 :20;
} __hethrsh_bits;
/* HET - HETXOR HR XOR Control Register */
typedef struct {
__REG32 HR_XOR_SHARE_0_1 :1;
__REG32 HR_XOR_SHARE_2_3 :1;
__REG32 HR_XOR_SHARE_4_5 :1;
__REG32 HR_XOR_SHARE_6_7 :1;
__REG32 HR_XOR_SHARE_8_9 :1;
__REG32 HR_XOR_SHARE_10_11:1;
__REG32 HR_XOR_SHARE_12_13:1;
__REG32 HR_XOR_SHARE_14_15:1;
__REG32 HR_XOR_SHARE_16_17:1;
__REG32 HR_XOR_SHARE_18_19:1;
__REG32 HR_XOR_SHARE_20_21:1;
__REG32 HR_XOR_SHARE_22_23:1;
__REG32 :20;
} __hetxor_bits;
/* SPI - SPICTRL1 SPI Control Register 1 */
typedef struct {
__REG32 CHARLEN :5;
__REG32 PRESCALE :8;
__REG32 :19;
} __spictrl1_bits;
/* SPI - SPICTRL2 SPI Control Register 2 */
typedef struct {
__REG32 PHASE :1;
__REG32 POLARITY :1;
__REG32 PWRDN :1;
__REG32 MASTER :1;
__REG32 SPIEN :1;
__REG32 CLKMOD :1;
__REG32 :26;
} __spictrl2_bits;
/* SPI - SPICTRL3 SPI Control Register 3 */
typedef struct {
__REG32 RXINTFLAG :1;
__REG32 RXINTEN :1;
__REG32 RCVR_OVRN :1;
__REG32 OVRNINTEN :1;
__REG32 :1;
__REG32 ENABLE_HIGH_Z :1;
__REG32 :26;
} __spictrl3_bits;
/* SPI - SPIDAT1 SPI Shift Register 0 */
typedef struct {
__REG32 SPIDAT0 :16;
__REG32 :16;
} __spidat0_bits;
/* SPI - SPIDAT1 SPI Shift Register 1 */
typedef struct {
__REG32 SPIDAT1 :16;
__REG32 :16;
} __spidat1_bits;
/* SPI - SPIBUF SPI Buffer Register */
typedef struct {
__REG32 SPIBUF :16;
__REG32 RXINTFLAG_IMG :1;
__REG32 RCVR_OVRN_IMG :1;
__REG32 :14;
} __spibuf_bits;
/* SPI - SPIEMU SPI Emulation Register */
typedef struct {
__REG32 SPIEMU :16;
__REG32 :16;
} __spiemu_bits;
/* SPI - SPIPC1 SPI Pin Control Register 1 */
typedef struct {
__REG32 ENA_DIR :1;
__REG32 CLK_DIR :1;
__REG32 SIMO_DIR :1;
__REG32 SOMI_DIR :1;
__REG32 SCS_DIR :1;
__REG32 :27;
} __spipc1_bits;
/* SPI - SPIPC2 SPI Pin Control Register 2 */
typedef struct {
__REG32 ENA_DIN :1;
__REG32 CLK_DIN :1;
__REG32 SIMO_DIN :1;
__REG32 SOMI_DIN :1;
__REG32 SCS_DIN :1;
__REG32 :27;
} __spipc2_bits;
/* SPI - SPIPC3 SPI Pin Control Register 3 */
typedef struct {
__REG32 ENA_DOUT :1;
__REG32 CLK_DOUT :1;
__REG32 SIMO_DOUT :1;
__REG32 SOMI_DOUT :1;
__REG32 SCS_DOUT :1;
__REG32 :27;
} __spipc3_bits;
/* SPI - SPIPC4 SPI Pin Control Register 4 */
typedef struct {
__REG32 ENA_DSET :1;
__REG32 CLK_DSET :1;
__REG32 SIMO_DSET :1;
__REG32 SOMI_DSET :1;
__REG32 SCS_DSET :1;
__REG32 :27;
} __spipc4_bits;
/* SPI - SPIPC5 SPI Pin Control Register 5 */
typedef struct {
__REG32 ENA_DCLR :1;
__REG32 CLK_DCLR :1;
__REG32 SIMO_DCLR :1;
__REG32 SOMI_DCLR :1;
__REG32 SCS_DCLR :1;
__REG32 :27;
} __spipc5_bits;
/* SPI - SPIPC6 SPI Pin Control Register 6 */
typedef struct {
__REG32 ENA_FUN :1;
__REG32 CLK_FUN :1;
__REG32 SIMO_FUN :1;
__REG32 SOMI_FUN :1;
__REG32 SCS_FUN :1;
__REG32 :27;
} __spipc6_bits;
/* SCI - SCICCR Communication Control Register */
typedef struct {
__REG8 CHAR0 :1;
__REG8 CHAR1 :1;
__REG8 CHAR2 :1;
__REG8 COMM_MODE :1;
__REG8 TIMING_MODE :1;
__REG8 PARITY_ENA :1;
__REG8 PARITY :1;
__REG8 STOP :1;
} __sciccr_bits;
/* SCI - SCICTL1 SCI Control Register 1 */
typedef struct {
__REG8 RXENA :1;
__REG8 RXWAKE :1;
__REG8 RXRDY :1;
__REG8 SLEEP :1;
__REG8 IDLE :1;
__REG8 :3;
} __scictl1_bits;
/* SCI - SCICTL2 SCI Control Register 2 */
typedef struct {
__REG8 TXENA :1;
__REG8 TXWAKE :1;
__REG8 TXRDY :1;
__REG8 TX_EMPTY :1;
__REG8 :2;
__REG8 LOOP_BACK :1;
__REG8 CONT :1;
} __scictl2_bits;
/* SCI - SCICTL3 SCI Control Register 3 */
typedef struct {
__REG8 RXERR_INT_ENA :1;
__REG8 BRKDT_INT_ENA :1;
__REG8 WAKEUP_INT_ENA :1;
__REG8 TX_ACTION_ENA :1;
__REG8 RX_ACTION_ENA :1;
__REG8 CLOCK :1;
__REG8 POWER_DOWN :1;
__REG8 SW_RESET :1;
} __scictl3_bits;
/* SCI - SCIRXST Receiver Status Register */
typedef struct {
__REG8 RXERR :1;
__REG8 BRKDT :1;
__REG8 WAKEUP :1;
__REG8 PE :1;
__REG8 OE :1;
__REG8 FE :1;
__REG8 :1;
__REG8 BUS_BUSY :1;
} __scirxst_bits;
/* SCI - SCIPC1 Pin Control Register 1 */
typedef struct {
__REG8 CLK_DATA_DIR :1;
__REG8 CLK_FUNC :1;
__REG8 CLK_DATA_OUT :1;
__REG8 CLK_DATA_IN :1;
__REG8 :4;
} __scipc1_bits;
/* SCI - SCIPC2 Pin Control Register 2 */
typedef struct {
__REG8 RX_DATA_DIR :1;
__REG8 RX_FUNC :1;
__REG8 RX_DATA_OUT :1;
__REG8 RX_DATA_IN :1;
__REG8 :4;
} __scipc2_bits;
/* SCI - SCIPC3 Pin Control Register 2 */
typedef struct {
__REG8 TX_DATA_DIR :1;
__REG8 TX_FUNC :1;
__REG8 TX_DATA_OUT :1;
__REG8 TX_DATA_IN :1;
__REG8 :4;
} __scipc3_bits;
/* MibADC - ADCR1 AD Control Register 1 */
typedef struct {
__REG16 PS :3;
__REG16 ACQ :2;
__REG16 ADC_EN :1;
__REG16 :2;
__REG16 PWR_DN :1;
__REG16 SELF_TST :1;
__REG16 HILO :1;
__REG16 BRIDGE_EN :1;
__REG16 CAL_ST :1;
__REG16 CAL_EN :1;
__REG16 :1;
__REG16 COS :1;
} __adccr1_bits;
/* MibADC - ADCR2 AD Control Register 2 */
typedef struct {
__REG16 ENA_G2_INT :1;
__REG16 FRZ_G2 :1;
__REG16 G2_MODE :1;
__REG16 ENA_G1_INT :1;
__REG16 FRZ_G1 :1;
__REG16 G1_MODE :1;
__REG16 :2;
__REG16 EV_EDG_SEL :1;
__REG16 ENA_EV_INT :1;
__REG16 FRZ_EV :1;
__REG16 EV_MODE :1;
__REG16 :4;
} __adccr2_bits;
/* MibADC - ADSR AD Status Register */
typedef struct {
__REG16 EV_END :1;
__REG16 G2_END :1;
__REG16 G1_END :1;
__REG16 :5;
__REG16 EV_STOP :1;
__REG16 G2_STOP :1;
__REG16 G1_STOP :1;
__REG16 EV_BUSY :1;
__REG16 G2_BUSY :1;
__REG16 G1_BUSY :1;
__REG16 :2;
} __adsr_bits;
/* MibADC - ADCALR Calibration and Offset Error Correction Register */
typedef struct {
__REG16 CALR :10;
__REG16 :6;
} __adcalr_bits;
/* MibADC - ADDR0 Digital Result Registers */
typedef struct {
__REG16 DT :10;
__REG16 :5;
__REG16 DT_ST :1;
} __addr_bits;
/* MibADC - ADEMDR0 Emulation Digital Result Registers */
typedef struct {
__REG16 EDT_9_0 :10;
__REG16 :5;
__REG16 EDT_ST :1;
} __ademdr_bits;
/* MibADC - ADMDR0 Emulation Digital Result Registers */
/* MibADC - ADBUFE AD Event FIFO Buffer */
typedef union {
ADEMDRx
struct {
__REG16 EDT_9_0 :10;
__REG16 :5;
__REG16 EDT_ST :1;
};
//ADBUFE
struct {
__REG16 EVDR :10;
__REG16 EVCHID :4;
__REG16 :1;
__REG16 EV_EMPTY :1;
};
} __ademdr014adbufe_bits;
typedef union{
/* Buffered mode */
/* ADEMDR4 Emulation Digital Result Registers */
struct {
__REG16 EDT_9_0 :10;
__REG16 :5;
__REG16 EDT_ST :1;
};
/* Compatibility mode */
/* ADBUF1 AD Group 1 FIFO Buffer */
struct {
__REG16 G1DR :10;
__REG16 G1CHID :4;
__REG16 :1;
__REG16 G1_EMPTY :1;
};
} __ademdr4adbuf1_bits;
typedef union{
/* Buffered mode */
/* ADEMDR8 ADMDR15 Emulation Digital Result Registers */
struct {
__REG16 EDT_9_0 :10;
__REG16 :5;
__REG16 EDT_ST :1;
};
/* Compatibility mode */
/* ADBUF2 AD Group 2 FIFO Buffer */
struct {
__REG16 G2DR :10;
__REG16 G2CHID :4;
__REG16 :1;
__REG16 G2_EMPTY :1;
};
} __ademdr815adbuf2_bits;
typedef union{
/* Buffered mode */
/* ADDR15 Digital Result Registers */
struct {
__REG16 DT :10;
__REG16 :5;
__REG16 DT_ST :1;
};
/* Compatibility mode */
/* ADBUF1 AD Group 1 FIFO Buffer */
struct {
__REG16 G1DR :10;
__REG16 G1CHID :4;
__REG16 :1;
__REG16 G1_EMPTY :1;
};
} __addr15ademubuf1_bits;
/* MibADC - ADCPCR Pin Control Register */
typedef struct {
__REG16 EVT_DIR :1;
__REG16 :1;
__REG16 EVT_OUT :1;
__REG16 EVT_IN :1;
__REG16 :12;
} __adcpcr_bits;
/* MibADC - ADBCR1 AD Buffer Control Register 1 */
typedef struct {
__REG16 BNDB :8;
__REG16 BNDA :7;
__REG16 BUFEN :1;
} __adbcr1_bits;
/* MibADC - ADBCR2 AD Buffer Control Register 2 */
typedef struct {
__REG16 BINDEND :3;
__REG16 :13;
} __adbcr2_bits;
/* MibADC - ADBCR3 AD Buffer Control Register 3 */
typedef struct {
__REG16 CHID :1;
__REG16 G2_8_BIT :1;
__REG16 G1_8_BIT :1;
__REG16 EV_8_BIT :1;
__REG16 :3;
__REG16 G2_BUF_INTEN :1;
__REG16 G1_BUF_INTEN :1;
__REG16 EV_BUF_INTEN :1;
__REG16 G2_OVR_INTEN :1;
__REG16 G1_OVR_INTEN :1;
__REG16 EV_OVR_INTEN :1;
__REG16 :3;
} __adbcr3_bits;
/* MibADC - ADBUFST AD Buffer Status Register */
typedef struct {
__REG16 G2_EMPTY :1;
__REG16 G1_EMPTY :1;
__REG16 EV_EMPTY :1;
__REG16 :1;
__REG16 G2_OVR_FLAG :1;
__REG16 G1_OVR_FLAG :1;
__REG16 EV_OVR_FLAG :1;
__REG16 :1;
__REG16 G2_INT_FLAG :1;
__REG16 G1_INT_FLAG :1;
__REG16 EV_INT_FLAG :1;
__REG16 :5;
} __adbufst_bits;
/* MibADC - ADTHREV AD Event Group Threshold Counter */
typedef struct {
__REG16 EVTHR :10;
__REG16 SIGN_EX :6;
} __adthrev_bits;
/* MibADC - ADTHRG1 AD Group 1 Threshold Counter */
typedef struct {
__REG16 G1THR :10;
__REG16 SIGN_EX :6;
} __adthrg1_bits;
/* MibADC - ADTHRG2 AD Group 2 Threshold Counter */
typedef struct {
__REG16 G2THR :10;
__REG16 SIGN_EX :6;
} __adthrg2_bits;
/* MibADC - ADSAMPEV AD Sample Time Event Register */
typedef struct {
__REG16 EVACQ :8;
__REG16 :7;
__REG16 SEN :1;
} __adsampev_bits;
/* MibADC - ADSAMP1 AD Sample Time Group 1 Register */
typedef struct {
__REG16 G1ACQ :8;
__REG16 :8;
} __adsamp1_bits;
/* MibADC - ADSAMP2 AD Sample Time Group 2 Register */
typedef struct {
__REG16 G2ACQ :8;
__REG16 :8;
} __adsamp2_bits;
/* MibADC - ADEVTSRC AD Event Source Register */
typedef struct {
__REG16 EVSRC :2;
__REG16 :2;
__REG16 G1SRC :2;
__REG16 :1;
__REG16 G1_EDG_SEL :1;
__REG16 G1_ENA :1;
__REG16 :7;
} __adevtsrc_bits;
/* ECP - ECPCTRL ECP Control Register */
typedef struct {
__REG16 ECPDIV :8;
__REG16 ECPCOS :1;
__REG16 :6;
__REG16 ECPEN :1;
} __ecpctrl_bits;
/* EBM - EBRWCR EBM Read/Write Control Register */
typedef struct {
__REG8 EBOE : 1;
__REG8 EBWR : 2;
__REG8 EBCS : 4;
__REG8 EBHOLD : 1;
} __ebrwcr_bits;
/* EBM - EBACR1 EBM Address Control Register 1 */
typedef struct {
__REG8 EBADDR : 6;
__REG8 EBWR : 2;
} __ebacr1_bits;
/* EBM - EBMCR1 EBM Control Register */
typedef struct {
__REG8 LPM :1;
__REG8 DSIZE :2;
__REG8 :3; /* must be 0 */
__REG8 :2;
} __ebmcr1_bits;
/* GIOPWDN GIO Power Down */
typedef struct {
__REG32 GIOPWDN :1;
__REG32 :31;
} __giopwdn_bits;
/* GIOENA1 GIO Interrupt Enable */
typedef struct {
__REG32 ENA_A :8;
__REG32 ENA_B :8;
__REG32 :16;
} __gioena1_bits;
/* GIOPOL1 GIO Interrupt Polarity */
typedef struct {
__REG32 POL_A :8;
__REG32 POL_B :8;
__REG32 :16;
} __giopol1_bits;
/* GIOFLG1 GIO Interrupt Flag */
typedef struct {
__REG32 FLG_A :8;
__REG32 FLG_B :8;
__REG32 :16;
} __gioflg1_bits;
/* GIOPRY1 GIO Interrupt Priority */
typedef struct {
__REG32 PRY_A :8;
__REG32 PRY_B :8;
__REG32 :16;
} __giopry1_bits;
/* GIOOFFA GIO Offset A */
typedef struct {
__REG32 GIOOFFA :7;
__REG32 :25;
} __giooffa_bits;
/* GIOEMUA GIO Emulation A */
typedef struct {
__REG32 GIOEMUA :7;
__REG32 :25;
} __gioemua_bits;
/* GIOOFFB GIO Offset B */
typedef struct {
__REG32 GIOOFFB :7;
__REG32 :25;
} __giooffb_bits;
/* GIOEMUB GIO Emulation B */
typedef struct {
__REG32 GIOEMUB :7;
__REG32 :25;
} __gioemub_bits;
/* GIODIRx GIO Data Direction */
typedef struct {
__REG32 GIODIR0 :1;
__REG32 GIODIR1 :1;
__REG32 GIODIR2 :1;
__REG32 GIODIR3 :1;
__REG32 GIODIR4 :1;
__REG32 GIODIR5 :1;
__REG32 GIODIR6 :1;
__REG32 GIODIR7 :1;
__REG32 :24;
} __giodir_bits;
/* GIODINx GIO Data Input */
typedef struct {
__REG32 GIODIN0 :1;
__REG32 GIODIN1 :1;
__REG32 GIODIN2 :1;
__REG32 GIODIN3 :1;
__REG32 GIODIN4 :1;
__REG32 GIODIN5 :1;
__REG32 GIODIN6 :1;
__REG32 GIODIN7 :1;
__REG32 :24;
} __giodin_bits;
/* GIODOUTx GIO Data Output */
typedef struct {
__REG32 GIODOUT0 :1;
__REG32 GIODOUT1 :1;
__REG32 GIODOUT2 :1;
__REG32 GIODOUT3 :1;
__REG32 GIODOUT4 :1;
__REG32 GIODOUT5 :1;
__REG32 GIODOUT6 :1;
__REG32 GIODOUT7 :1;
__REG32 :24;
} __giodout_bits;
/* GIODSETx GIO Data Set */
typedef struct {
__REG32 GIODSET0 :1;
__REG32 GIODSET1 :1;
__REG32 GIODSET2 :1;
__REG32 GIODSET3 :1;
__REG32 GIODSET4 :1;
__REG32 GIODSET5 :1;
__REG32 GIODSET6 :1;
__REG32 GIODSET7 :1;
__REG32 :24;
} __giodset_bits;
/* GIODCLRx GIO Data Clear */
typedef struct {
__REG32 GIODCLR0 :1;
__REG32 GIODCLR1 :1;
__REG32 GIODCLR2 :1;
__REG32 GIODCLR3 :1;
__REG32 GIODCLR4 :1;
__REG32 GIODCLR5 :1;
__REG32 GIODCLR6 :1;
__REG32 GIODCLR7 :1;
__REG32 :24;
} __giodclr_bits;
/* CAN/HECC - CANGAM Global acceptance mask */
typedef struct {
__REG32 GAM :29;
__REG32 :2;
__REG32 AMI :1;
} __cangam_bits;
/* CAN/HECC - CANMC Master control */
typedef struct {
__REG32 MBNR :5;
__REG32 SRES :1;
__REG32 STM :1;
__REG32 ABO :1;
__REG32 CDR :1;
__REG32 WUBA :1;
__REG32 DBO :1;
__REG32 PDR :1;
__REG32 CCR :1;
__REG32 SCM :1;
__REG32 LNTM :1;
__REG32 LNTC :1;
__REG32 :16;
} __canmc_bits;
/* CAN/HECC - CANBTC Bit-timing configuration */
typedef struct {
__REG32 TSEG2 :3;
__REG32 TSEG1 :4;
__REG32 SAM :1;
__REG32 SJW :2;
__REG32 ERM :1;
__REG32 :5;
__REG32 BRP :8;
__REG32 :8;
} __canbtc_bits;
/* CAN/HECC - CANES Error and status */
typedef struct {
__REG32 TM :1;
__REG32 RM :1;
__REG32 :1;
__REG32 PDA :1;
__REG32 CCE :1;
__REG32 SMA :1;
__REG32 :10;
__REG32 EW :1;
__REG32 EP :1;
__REG32 BO :1;
__REG32 ACKE :1;
__REG32 SE :1;
__REG32 CRCE :1;
__REG32 SA1 :1;
__REG32 BE :1;
__REG32 FE :1;
__REG32 :7;
} __canes_bits;
/* CAN/HECC - CANTEC Transmit error counter */
typedef struct {
__REG32 TEC :8;
__REG32 :24;
} __cantec_bits;
/* CAN/HECC - CANREC Receive error counter */
typedef struct {
__REG32 REC :8;
__REG32 :24;
} __canrec_bits;
/* CAN/HECC - CANGIFx Global interrupt flag */
typedef struct {
__REG32 MIV_3_0 :4;
__REG32 MIV_4 :1;
__REG32 :3;
__REG32 WLIF :1;
__REG32 EPIF :1;
__REG32 BOIF :1;
__REG32 RMLIF :1;
__REG32 WUIF :1;
__REG32 WDIF :1;
__REG32 AAIF :1;
__REG32 GMIF :1;
__REG32 TCOIF :1;
__REG32 MAIF :1;
__REG32 :14;
} __cangif_bits;
/* CAN/HECC - CANGIM Global interrupt mask */
typedef struct {
__REG32 I0EN :1;
__REG32 I1EN :1;
__REG32 SIL :1;
__REG32 :5;
__REG32 WLIM :1;
__REG32 EPIM :1;
__REG32 BOIM :1;
__REG32 RMLIM :1;
__REG32 WUIM :1;
__REG32 WDIM :1;
__REG32 AAIM :1;
__REG32 :1;
__REG32 TCOIM :1;
__REG32 MAIM :1;
__REG32 :14;
} __cangim_bits;
/* CAN/HECC - CANTIOC TX I/O control */
typedef struct {
__REG32 TXIN :1;
__REG32 TXOUT :1;
__REG32 TXDIR :1;
__REG32 TXFUNC :1;
__REG32 :28;
} __cantioc_bits;
/* CAN/HECC - CANRIOC RX I/O control */
typedef struct {
__REG32 RXIN :1;
__REG32 RXOUT :1;
__REG32 RXDIR :1;
__REG32 RXFUNC :1;
__REG32 :28;
} __canrioc_bits;
/* CAN/HECC RAM - Message Identifier Register (MID) */
typedef struct {
__REG32 ID :29;
__REG32 AAM : 1;
__REG32 AME : 1;
__REG32 IDE : 1;
} __mid_bits;
/* CAN/HECC RAM - Message Control Field Register (MCF) */
typedef struct {
__REG32 DLC : 4;
__REG32 RTR : 1;
__REG32 : 3;
__REG32 TPL : 6;
__REG32 :18;
} __mcf_bits;
/* I2COAR I2C Own Address Register */
typedef struct {
__REG16 OA :10;
__REG16 :6;
} __i2coar_bits;
/* I2CIMR I2C Interrupt Mask/Status Register */
typedef struct {
__REG16 ALEN :1;
__REG16 NACKEN :1;
__REG16 ARDYEN :1;
__REG16 RXRDYEN :1;
__REG16 TXRDYEN :1;
__REG16 SCDEN :1;
__REG16 AASEN :1;
__REG16 :9;
} __i2cimr_bits;
/* I2CISR I2C Interrupt Status Register */
typedef struct {
__REG16 AL :1;
__REG16 NACK :1;
__REG16 ARDY :1;
__REG16 RXRDY :1;
__REG16 TXRDY :1;
__REG16 SCD :1;
__REG16 :2;
__REG16 AD0 :1;
__REG16 AAS :1;
__REG16 XSMT :1;
__REG16 RSFULL :1;
__REG16 BB :1;
__REG16 NACKSNT :1;
__REG16 SDIR :1;
__REG16 :1;
} __i2csr_bits;
/* I2CDRR I2C Data Receive Register */
typedef struct {
__REG16 DATARX :8;
__REG16 :8;
} __i2cdrr_bits;
/* I2CSAR I2C Slave Address Register */
typedef struct {
__REG16 SA :10;
__REG16 :6;
} __i2csar_bits;
/* I2CDXR I2C Data Transmit Register */
typedef struct {
__REG16 DATATX :8;
__REG16 :8;
} __i2cdxr_bits;
/* I2CMDR I2C Mode Register */
typedef struct {
__REG16 BC :3;
__REG16 FDF :1;
__REG16 STB :1;
__REG16 nIRS :1;
__REG16 DLB :1;
__REG16 RM :1;
__REG16 XA :1;
__REG16 TRX :1;
__REG16 MST :1;
__REG16 STP :1;
__REG16 LPM :1;
__REG16 STT :1;
__REG16 FREE :1;
__REG16 NACKMOD :1;
} __i2cmdr_bits;
/* I2CIVR I2C Interrupt Vector Register */
typedef struct {
__REG16 INTCODE :3;
__REG16 :5;
__REG16 TESTMD :4;
__REG16 :4;
} __i2civr_bits;
/* I2CEMR I2C Extended Mode Register */
typedef struct {
__REG16 BCM :1;
__REG16 :15;
} __i2cemr_bits;
/* I2CPSC I2C Prescale Register */
typedef struct {
__REG16 PSC :8;
__REG16 :8;
} __i2cpsc_bits;
/* I2CDIR I2C Data Direction Register */
typedef struct {
__REG16 SCLDIR :1;
__REG16 SDADIR :1;
__REG16 SCLFUNC :1;
__REG16 SDAFUNC :1;
__REG16 RXDMAEN :1;
__REG16 TXDMAEN :1;
__REG16 :10;
} __i2cdir_bits;
/* I2CDOUTP I2C Data Out Register */
typedef struct {
__REG16 SCLOUT :1;
__REG16 SDAOUT :1;
__REG16 :14;
} __i2cdoutp_bits;
/* I2CDINP I2C Data Input Register */
typedef struct {
__REG16 SCLIN :1;
__REG16 SDAIN :1;
__REG16 :14;
} __i2cdinp_bits;
/* I2CPFNC I2C Function Register */
typedef struct {
__REG16 PFUNC :1;
__REG16 :15;
} __i2cpgnc_bits;
/* I2CPDIR I2CPin Direction Register */
typedef struct {
__REG16 SCLDIR :1;
__REG16 SDADIR :1;
__REG16 :14;
} __i2cpdir_bits;
/* I2CDIN I2C Data Input Register */
typedef struct {
__REG16 SCLIN :1;
__REG16 SDAIN :1;
__REG16 :14;
} __i2cdin_bits;
/* I2CDOUT I2C Data Output Register */
typedef struct {
__REG16 SCLOUT :1;
__REG16 SDAOUT :1;
__REG16 :14;
} __i2cdout_bits;
/* I2CDSET I2C Data Set Register */
typedef struct {
__REG16 SCLSET :1;
__REG16 SDASET :1;
__REG16 :14;
} __i2cdset_bits;
/* I2CDCLR I2C Data Clear Register */
typedef struct {
__REG16 SCLCLR :1;
__REG16 SDACLR :1;
__REG16 :14;
} __i2cdclr_bits;
/* I2CPID1 I2C Peripheral ID Register 1 */
typedef struct {
__REG16 REVISION :8;
__REG16 CLASS :8;
} __i2cpid1_bits;
/* I2CPID2 I2C Peripheral ID Register 2 */
typedef struct {
__REG16 TYPE :8;
__REG16 :8;
} __i2cpid2_bits;
/* FMBAC1 Bank Access Control Register 1 */
typedef struct {
__REG16 BNKPWR :2;
__REG16 BSTDBY :6;
__REG16 BAGP :8;
} __fmbac1_bits;
/* FMBAC2 Bank Access Control Register 2 */
typedef struct {
__REG16 WAIT_3_0 :4;
__REG16 WAIT_7_4 :4;
__REG16 BSLEEP :7;
__REG16 OTPPROTDIS :1;
} __fmbac2_bits;
/* FMBRDY Bank Ready Register */
typedef struct {
__REG16 :5;
__REG16 BANKRDY :1;
__REG16 :10;
} __fmbrdy_bits;
/* FMREGOPT Option Control Register */
typedef struct {
__REG32 ENPIPE :1;
__REG32 READOTP :1;
__REG32 RDMRGN0 :1;
__REG32 RDMRGN1 :1;
__REG32 :28;
} __fmregopt_bits;
/* FMBBUSY Bank Busy Register */
typedef struct {
__REG32 BUSY :8;
__REG32 :7;
__REG32 PROTL2DIS :1;
__REG32 :16;
} __fmbbusy_bits;
/* FMPRDY Pump Ready Register */
typedef struct {
__REG16 :9;
__REG16 PUMPRDY :1;
__REG16 :6;
} __fmprdy_bits;
/* FMMAC1 Module Access Control Register 1 */
typedef struct {
__REG16 PSLEEP :15;
__REG16 PROTL1DIS :1;
} __fmmac1_bits;
/* FMMAC2 Module Access Control Register 2 */
typedef struct {
__REG16 BANK :3;
__REG16 PMPPWR :2;
__REG16 PSTDBY :11;
} __fmmac2_bits;
/* FMMSTAT Module Status Register */
typedef struct {
__REG16 SLOCK :1;
__REG16 PSUSP :1;
__REG16 ESUSP :1;
__REG16 _3VSTAT :1; /* 3VSTAT (symbols cannot start with a digit) */
__REG16 CSTAT :1;
__REG16 INVDAT :1;
__REG16 PGM :1;
__REG16 ERS :1;
__REG16 BUSY :1;
__REG16 :7;
} __fmmstat_bits;
#endif /* __IAR_SYSTEMS_ICC__ */
/* Declarations common to compiler and assembler *********************************/
/***************************************************************************
**
** System module control (SMC)
**
***************************************************************************/
__IO_REG32_BIT(SMCR0, 0xfffffd00,__READ_WRITE,__smcr0_bits);
__IO_REG32_BIT(SMCR1, 0xfffffd04,__READ_WRITE,__smcrx_bits);
__IO_REG32_BIT(SMCR2, 0xfffffd08,__READ_WRITE,__smcrx_bits);
__IO_REG32_BIT(SMCR3, 0xfffffd0c,__READ_WRITE,__smcrx_bits);
__IO_REG32_BIT(SMCR4, 0xfffffd10,__READ_WRITE,__smcrx_bits);
__IO_REG32_BIT(SMCR5, 0xfffffd14,__READ_WRITE,__smcrx_bits);
__IO_REG32_BIT(SMCR6, 0xfffffd18,__READ_WRITE,__smcrx_bits);
__IO_REG32_BIT(SMCR7, 0xfffffd1c,__READ_WRITE,__smcrx_bits);
__IO_REG32_BIT(SMCR8, 0xfffffd20,__READ_WRITE,__smcrx_bits);
__IO_REG32_BIT(SMCR9, 0xfffffd24,__READ_WRITE,__smcrx_bits);
__IO_REG32_BIT(WCR0, 0xfffffd2c,__READ_WRITE,__wcr_bits);
__IO_REG32_BIT(PLR, 0xfffffd34,__READ_WRITE,__plr_bits);
__IO_REG32_BIT(PPROT, 0xfffffd38,__READ_WRITE,__pprot_bits);
__IO_REG32_BIT(MFBAHR0, 0xfffffe00,__READ_WRITE,__mfbahr_bits);
__IO_REG32_BIT(MFBALR0, 0xfffffe04,__READ_WRITE,__mfbalr0_bits);
__IO_REG32_BIT(MFBAHR1, 0xfffffe08,__READ_WRITE,__mfbahr_bits);
__IO_REG32_BIT(MFBALR1, 0xfffffe0c,__READ_WRITE,__mfbalrx_bits);
__IO_REG32_BIT(MFBAHR2, 0xfffffe10,__READ_WRITE,__mfbahr_bits);
__IO_REG32_BIT(MFBALR2, 0xfffffe14,__READ_WRITE,__mfbalrx_bits);
__IO_REG32_BIT(MFBAHR3, 0xfffffe18,__READ_WRITE,__mfbahr_bits);
__IO_REG32_BIT(MFBALR3, 0xfffffe1c,__READ_WRITE,__mfbalrx_bits);
__IO_REG32_BIT(MFBAHR4, 0xfffffe20,__READ_WRITE,__mfbahr_bits);
__IO_REG32_BIT(MFBALR4, 0xfffffe24,__READ_WRITE,__mfbalrx_bits);
__IO_REG32_BIT(MFBAHR5, 0xfffffe28,__READ_WRITE,__mfbahr_bits);
__IO_REG32_BIT(MFBALR5, 0xfffffe2c,__READ_WRITE,__mfbalrx_bits);
__IO_REG32_BIT(MCBAHR0, 0xfffffe30,__READ_WRITE,__mcbahr_bits);
__IO_REG32_BIT(MCBALR0, 0xfffffe34,__READ_WRITE,__mcbalr_bits);
__IO_REG32_BIT(MCBAHR1, 0xfffffe38,__READ_WRITE,__mcbahr_bits);
__IO_REG32_BIT(MCBALR1, 0xfffffe3c,__READ_WRITE,__mcbalr_bits);
__IO_REG32_BIT(MCBAHR2, 0xfffffe40,__READ_WRITE,__mcbahr_bits);
__IO_REG32_BIT(MCBALR2, 0xfffffe44,__READ_WRITE,__mcbalr_bits);
__IO_REG32_BIT(MCBAHR3, 0xfffffe48,__READ_WRITE,__mcbahr_bits);
__IO_REG32_BIT(MCBALR3, 0xfffffe4c,__READ_WRITE,__mcbalr_bits);
__IO_REG32_BIT(MCBAHR4, 0xfffffe50,__READ_WRITE,__mcbahr_bits);
__IO_REG32_BIT(MCBALR4, 0xfffffe54,__READ_WRITE,__mcbalr_bits);
__IO_REG32_BIT(MCBAHR5, 0xfffffe58,__READ_WRITE,__mcbahr_bits);
__IO_REG32_BIT(MCBALR5, 0xfffffe5c,__READ_WRITE,__mcbalr_bits);
__IO_REG32_BIT(RTICNTR, 0xffffff00,__READ_WRITE,__rticntr_bits);
__IO_REG32_BIT(RTIPCTL, 0xffffff04,__READ_WRITE,__rtipctl_bits);
__IO_REG32_BIT(RTICNTL, 0xffffff08,__READ_WRITE,__rticntl_bits);
__IO_REG32( WKEY, 0xffffff0c,__READ_WRITE);
__IO_REG32_BIT(RTICMP1, 0xffffff10,__READ_WRITE,__rticmp1_bits);
__IO_REG32_BIT(RTICMP2, 0xffffff14,__READ_WRITE,__rticmp2_bits);
__IO_REG32_BIT(RTICINT, 0xffffff18,__READ_WRITE,__rticint_bits);
__IO_REG32_BIT(RTICNTEN, 0xffffff1c,__READ_WRITE,__rticnten_bits);
__IO_REG32_BIT(IRQIVEC, 0xffffff20,__READ_WRITE,__irqivec_bits);
__IO_REG32_BIT(FIQIVEC, 0xffffff24,__READ_WRITE,__fiqivec_bits);
__IO_REG32_BIT(CIMIVEC, 0xffffff28,__READ_WRITE,__cimivec_bits);
__IO_REG32( FIRQPR, 0xffffff2c,__READ_WRITE);
__IO_REG32( INTREQ, 0xffffff30,__READ_WRITE);
__IO_REG32( REQMASK, 0xffffff34,__READ_WRITE);
__IO_REG32_BIT(SSIF, 0xfffffff8,__READ_WRITE,__ssif_bits);
__IO_REG32_BIT(SSIR, 0xfffffffc,__READ_WRITE,__ssir_bits);
__IO_REG32( CPUPSA, 0xffffff40,__READ_WRITE);
__IO_REG32_BIT(PSAENABLE,0xffffff50,__READ_WRITE,__psaenable_bits);
__IO_REG32_BIT(PCR, 0xfffffd30,__READ_WRITE,__pcr_bits);
__IO_REG32_BIT(CLKCNTL, 0xffffffd0,__READ_WRITE,__clkcntl_bits);
__IO_REG32_BIT(GCR, 0xffffffdc,__READ_WRITE,__gcr_bits);
__IO_REG32_BIT(SYSECR, 0xffffffe0,__READ_WRITE,__sysecr_bits);
__IO_REG32_BIT(SYSESR, 0xffffffe4,__READ_WRITE,__sysesr_bits);
__IO_REG32_BIT(ABRTESR, 0xffffffe8,__READ_WRITE,__abrtesr_bits);
__IO_REG32_BIT(GLBSTAT, 0xffffffec,__READ_WRITE,__glbstat_bits);
__IO_REG32_BIT(DEV, 0xfffffff0,__READ_WRITE,__dev_bits);
/***************************************************************************
**
** IEM
**
***************************************************************************/
__IO_REG32_BIT(INTPEND0, 0xfffffc00, __READ , __intpend0_bits);
__IO_REG32_BIT(INTPEND1, 0xfffffc04, __READ , __intpend1_bits);
__IO_REG32_BIT(INTCTRL0, 0xfffffc20, __READ_WRITE, __intctrl0_bits);
__IO_REG32_BIT(INTCTRL1, 0xfffffc24, __READ_WRITE, __intctrl1_bits);
__IO_REG32_BIT(INTCTRL2, 0xfffffc28, __READ_WRITE, __intctrl2_bits);
__IO_REG32_BIT(INTCTRL3, 0xfffffc2c, __READ_WRITE, __intctrl3_bits);
__IO_REG32_BIT(INTCTRL4, 0xfffffc30, __READ_WRITE, __intctrl4_bits);
__IO_REG32_BIT(INTCTRL5, 0xfffffc34, __READ_WRITE, __intctrl5_bits);
__IO_REG32_BIT(INTCTRL6, 0xfffffc38, __READ_WRITE, __intctrl6_bits);
__IO_REG32_BIT(INTCTRL7, 0xfffffc3c, __READ_WRITE, __intctrl7_bits);
__IO_REG32_BIT(INTCTRL8, 0xfffffc40, __READ_WRITE, __intctrl8_bits);
__IO_REG32_BIT(INTCTRL9, 0xfffffc44, __READ_WRITE, __intctrl9_bits);
__IO_REG32_BIT(INTCTRL10, 0xfffffc48, __READ_WRITE, __intctrl10_bits);
__IO_REG32_BIT(INTCTRL11, 0xfffffc4c, __READ_WRITE, __intctrl11_bits);
__IO_REG32_BIT(INTCTRL12, 0xfffffc50, __READ_WRITE, __intctrl12_bits);
__IO_REG32_BIT(INTCTRL13, 0xfffffc54, __READ_WRITE, __intctrl13_bits);
__IO_REG32_BIT(INTCTRL14, 0xfffffc58, __READ_WRITE, __intctrl14_bits);
__IO_REG32_BIT(INTCTRL15, 0xfffffc5c, __READ_WRITE, __intctrl15_bits);
/***************************************************************************
**
** MSM 1 - Memory Security Module 1
**
***************************************************************************/
__IO_REG32( MSMKEY0, 0xfffff700, __READ_WRITE);
__IO_REG32( MSMKEY1, 0xfffff704, __READ_WRITE);
__IO_REG32( MSMKEY2, 0xfffff708, __READ_WRITE);
__IO_REG32( MSMKEY3, 0xfffff70c, __READ_WRITE);
__IO_REG32_BIT( MSMSCR, 0xfffff724, __READ_WRITE, __msmscr_bits);
__IO_REG32( MSMPWL0, 0x0000ffe0, __READ_WRITE); // password for first MSM
__IO_REG32( MSMPWL1, 0x0000ffe4, __READ_WRITE);
__IO_REG32( MSMPWL2, 0x0000ffe8, __READ_WRITE);
__IO_REG32( MSMPWL3, 0x0000ffec, __READ_WRITE);
/***************************************************************************
**
** MPU
**
***************************************************************************/
__IO_REG32_BIT(MPUAHR0, 0xffe84000,__READ_WRITE,__mpuahr_bits);
__IO_REG32_BIT(MPUALR0, 0xffe84004,__READ_WRITE,__mpualr_bits);
__IO_REG32_BIT(MPUAHR1, 0xffe84008,__READ_WRITE,__mpuahr_bits);
__IO_REG32_BIT(MPUALR1, 0xffe8400c,__READ_WRITE,__mpualr_bits);
__IO_REG32_BIT(MPUAHR2, 0xffe84010,__READ_WRITE,__mpuahr_bits);
__IO_REG32_BIT(MPUALR2, 0xffe84014,__READ_WRITE,__mpualr_bits);
__IO_REG32_BIT(MPUAHR3, 0xffe84018,__READ_WRITE,__mpuahr_bits);
__IO_REG32_BIT(MPUALR3, 0xffe8401c,__READ_WRITE,__mpualr_bits);
__IO_REG32_BIT(MPUCTRL, 0xffe84020,__READ_WRITE,__mpuctrl_bits);
/***************************************************************************
**
** HET
**
***************************************************************************/
__IO_REG32_BIT(HETGCR, 0xfff7fc00,__READ_WRITE,__hetgcr_bits);
__IO_REG32_BIT(HETPFR, 0xfff7fc04,__READ_WRITE,__hetpfr_bits);
__IO_REG32_BIT(HETADDR, 0xfff7fc08,__READ_WRITE,__hetaddr_bits);
__IO_REG32_BIT(HETOFF1, 0xfff7fc0c,__READ_WRITE,__hetoff_bits);
__IO_REG32_BIT(HETOFF2, 0xfff7fc10,__READ_WRITE,__hetoff_bits);
__IO_REG32_BIT(HETEXC1, 0xfff7fc14,__READ_WRITE,__hetexc1_bits);
__IO_REG32_BIT(HETEXC2, 0xfff7fc18,__READ_WRITE,__hetexc2_bits);
__IO_REG32( HETPRY, 0xfff7fc1c,__READ_WRITE);
__IO_REG32( HETFLG, 0xfff7fc20,__READ_WRITE);
__IO_REG32_BIT(HETHRSH, 0xfff7fc2c,__READ_WRITE,__hethrsh_bits);
__IO_REG32_BIT(HETXOR, 0xfff7fc30,__READ_WRITE,__hetxor_bits);
__IO_REG32( HETDIR, 0xfff7fc34,__READ_WRITE);
__IO_REG32( HETDIN, 0xfff7fc38,__READ_WRITE);
__IO_REG32( HETDOUT, 0xfff7fc3c,__READ_WRITE);
__IO_REG32( HETDSET, 0xfff7fc40,__READ_WRITE);
__IO_REG32( HETDCLR, 0xfff7fc44,__READ_WRITE);
/***************************************************************************
**
** SPI1
**
***************************************************************************/
__IO_REG32_BIT(SPI1CTRL1,0xfff7f800,__READ_WRITE,__spictrl1_bits);
__IO_REG32_BIT(SPI1CTRL2,0xfff7f804,__READ_WRITE,__spictrl2_bits);
__IO_REG32_BIT(SPI1CTRL3,0xfff7f808,__READ_WRITE,__spictrl3_bits);
__IO_REG32_BIT(SPI1DAT0, 0xfff7f80C,__READ_WRITE,__spidat0_bits);
__IO_REG32_BIT(SPI1DAT1, 0xfff7f810,__READ_WRITE,__spidat1_bits);
__IO_REG32_BIT(SPI1BUF, 0xfff7f814,__READ_WRITE,__spibuf_bits);
__IO_REG32_BIT(SPI1EMU, 0xfff7f818,__READ_WRITE,__spiemu_bits);
__IO_REG32_BIT(SPI1PC1, 0xfff7f81c,__READ_WRITE,__spipc1_bits);
__IO_REG32_BIT(SPI1PC2, 0xfff7f820,__READ_WRITE,__spipc2_bits);
__IO_REG32_BIT(SPI1PC3, 0xfff7f824,__READ_WRITE,__spipc3_bits);
__IO_REG32_BIT(SPI1PC4, 0xfff7f828,__READ_WRITE,__spipc4_bits);
__IO_REG32_BIT(SPI1PC5, 0xfff7f82c,__READ_WRITE,__spipc5_bits);
__IO_REG32_BIT(SPI1PC6, 0xfff7f830,__READ_WRITE,__spipc6_bits);
/***************************************************************************
**
** SPI2
**
***************************************************************************/
__IO_REG32_BIT(SPI2CTRL1,0xfff7d400,__READ_WRITE,__spictrl1_bits);
__IO_REG32_BIT(SPI2CTRL2,0xfff7d404,__READ_WRITE,__spictrl2_bits);
__IO_REG32_BIT(SPI2CTRL3,0xfff7d408,__READ_WRITE,__spictrl3_bits);
__IO_REG32_BIT(SPI2DAT0, 0xfff7d40c,__READ_WRITE,__spidat0_bits);
__IO_REG32_BIT(SPI2DAT1, 0xfff7d410,__READ_WRITE,__spidat1_bits);
__IO_REG32_BIT(SPI2BUF, 0xfff7d414,__READ_WRITE,__spibuf_bits);
__IO_REG32_BIT(SPI2EMU, 0xfff7d418,__READ_WRITE,__spiemu_bits);
__IO_REG32_BIT(SPI2PC1, 0xfff7d41c,__READ_WRITE,__spipc1_bits);
__IO_REG32_BIT(SPI2PC2, 0xfff7d420,__READ_WRITE,__spipc2_bits);
__IO_REG32_BIT(SPI2PC3, 0xfff7d424,__READ_WRITE,__spipc3_bits);
__IO_REG32_BIT(SPI2PC4, 0xfff7d428,__READ_WRITE,__spipc4_bits);
__IO_REG32_BIT(SPI2PC5, 0xfff7d42c,__READ_WRITE,__spipc5_bits);
__IO_REG32_BIT(SPI2PC6, 0xfff7d430,__READ_WRITE,__spipc6_bits);
/***************************************************************************
**
** SCI1
**
***************************************************************************/
__IO_REG8_BIT(SCI1CCR, 0xfff7f403,__READ_WRITE,__sciccr_bits);
__IO_REG8_BIT(SCI1CTL1, 0xfff7f407,__READ_WRITE,__scictl1_bits);
__IO_REG8_BIT(SCI1CTL2, 0xfff7f40b,__READ_WRITE,__scictl2_bits);
__IO_REG8_BIT(SCI1CTL3, 0xfff7f40f,__READ_WRITE,__scictl3_bits);
__IO_REG8_BIT(SCI1RXST, 0xfff7f413,__READ_WRITE,__scirxst_bits);
__IO_REG8( SCI1HBAUD, 0xfff7f417,__READ_WRITE);
__IO_REG8( SCI1MBAUD, 0xfff7f41b,__READ_WRITE);
__IO_REG8( SCI1LBAUD, 0xfff7f41f,__READ_WRITE);
__IO_REG8( SCI1RXEMU, 0xfff7f423,__READ_WRITE);
__IO_REG8( SCI1RXBUF, 0xfff7f427,__READ_WRITE);
__IO_REG8( SCI1TXBUF, 0xfff7f42b,__READ_WRITE);
__IO_REG8_BIT(SCI1PC1, 0xfff7f42f,__READ_WRITE,__scipc1_bits);
__IO_REG8_BIT(SCI1PC2, 0xfff7f433,__READ_WRITE,__scipc2_bits);
__IO_REG8_BIT(SCI1PC3, 0xfff7f437,__READ_WRITE,__scipc3_bits);
/***************************************************************************
**
** SCI2
**
***************************************************************************/
__IO_REG8_BIT(SCI2CCR, 0xfff7f503,__READ_WRITE,__sciccr_bits);
__IO_REG8_BIT(SCI2CTL1, 0xfff7f507,__READ_WRITE,__scictl1_bits);
__IO_REG8_BIT(SCI2CTL2, 0xfff7f50b,__READ_WRITE,__scictl2_bits);
__IO_REG8_BIT(SCI2CTL3, 0xfff7f50f,__READ_WRITE,__scictl3_bits);
__IO_REG8_BIT(SCI2RXST, 0xfff7f513,__READ_WRITE,__scirxst_bits);
__IO_REG8( SCI2HBAUD, 0xfff7f517,__READ_WRITE);
__IO_REG8( SCI2MBAUD, 0xfff7f51b,__READ_WRITE);
__IO_REG8( SCI2LBAUD, 0xfff7f51f,__READ_WRITE);
__IO_REG8( SCI2RXEMU, 0xfff7f523,__READ_WRITE);
__IO_REG8( SCI2RXBUF, 0xfff7f527,__READ_WRITE);
__IO_REG8( SCI2TXBUF, 0xfff7f52b,__READ_WRITE);
__IO_REG8_BIT(SCI2PC1, 0xfff7f52f,__READ_WRITE,__scipc1_bits);
__IO_REG8_BIT(SCI2PC2, 0xfff7f533,__READ_WRITE,__scipc2_bits);
__IO_REG8_BIT(SCI2PC3, 0xfff7f537,__READ_WRITE,__scipc3_bits);
/***************************************************************************
**
** SCI3
**
***************************************************************************/
__IO_REG8_BIT(SCI3CCR, 0xfff7f603,__READ_WRITE,__sciccr_bits);
__IO_REG8_BIT(SCI3CTL1, 0xfff7f607,__READ_WRITE,__scictl1_bits);
__IO_REG8_BIT(SCI3CTL2, 0xfff7f60b,__READ_WRITE,__scictl2_bits);
__IO_REG8_BIT(SCI3CTL3, 0xfff7f60f,__READ_WRITE,__scictl3_bits);
__IO_REG8_BIT(SCI3RXST, 0xfff7f613,__READ_WRITE,__scirxst_bits);
__IO_REG8( SCI3HBAUD, 0xfff7f617,__READ_WRITE);
__IO_REG8( SCI3MBAUD, 0xfff7f61b,__READ_WRITE);
__IO_REG8( SCI3LBAUD, 0xfff7f61f,__READ_WRITE);
__IO_REG8( SCI3RXEMU, 0xfff7f623,__READ_WRITE);
__IO_REG8( SCI3RXBUF, 0xfff7f627,__READ_WRITE);
__IO_REG8( SCI3TXBUF, 0xfff7f62b,__READ_WRITE);
__IO_REG8_BIT(SCI3PC1, 0xfff7f62f,__READ_WRITE,__scipc1_bits);
__IO_REG8_BIT(SCI3PC2, 0xfff7f633,__READ_WRITE,__scipc2_bits);
__IO_REG8_BIT(SCI3PC3, 0xfff7f637,__READ_WRITE,__scipc3_bits);
/***************************************************************************
**
** MibADC
**
***************************************************************************/
__IO_REG16_BIT(ADCR1, 0xfff7f002,__READ_WRITE,__adccr1_bits);
__IO_REG16_BIT(ADCR2, 0xfff7f006,__READ_WRITE,__adccr2_bits);
__IO_REG16_BIT(ADSR, 0xfff7f00a,__READ_WRITE,__adsr_bits);
__IO_REG16( ADEISR, 0xfff7f00e,__READ_WRITE);
__IO_REG16( ADISR1, 0xfff7f012,__READ_WRITE);
__IO_REG16( ADISR2, 0xfff7f016,__READ_WRITE);
__IO_REG16_BIT(ADCALR, 0xfff7f01a,__READ_WRITE,__adcalr_bits);
__IO_REG16_BIT(ADDR0, 0xfff7f01e,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR0, 0xfff7f022,__READ_WRITE,__ademdr014adbufe_bits);
__IO_REG16_BIT(ADDR1, 0xfff7f026,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR1, 0xfff7f02a,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR2, 0xfff7f02e,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR2, 0xfff7f032,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR3, 0xfff7f036,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR3, 0xfff7f03a,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR4, 0xfff7f03e,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR4, 0xfff7f042,__READ_WRITE,__ademdr4adbuf1_bits);
__IO_REG16_BIT(ADDR5, 0xfff7f046,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR5, 0xfff7f04a,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR6, 0xfff7f04e,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR6, 0xfff7f052,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR7, 0xfff7f056,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR7, 0xfff7f05a,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR8, 0xfff7f05e,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR8, 0xfff7f062,__READ_WRITE,__ademdr815adbuf2_bits);
__IO_REG16_BIT(ADDR9, 0xfff7f066,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR9, 0xfff7f06a,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR10, 0xfff7f06e,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR10, 0xfff7f072,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR11, 0xfff7f076,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR11, 0xfff7f07a,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR12, 0xfff7f07e,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR12, 0xfff7f082,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR13, 0xfff7f086,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR13, 0xfff7f08a,__READ_WRITE,__ademdr_bits);
__IO_REG16_BIT(ADDR14, 0xfff7f08e,__READ_WRITE,__addr_bits);
__IO_REG16_BIT(ADEMDR14, 0xfff7f092,__READ_WRITE,__ademdr014adbufe_bits);
__IO_REG16_BIT(ADDR15, 0xfff7f096,__READ_WRITE,__addr15ademubuf1_bits);
__IO_REG16_BIT(ADEMDR15, 0xfff7f09a,__READ_WRITE,__ademdr815adbuf2_bits);
/*
* These registers are used in buffered mode only. They have the same
* addresses as some of the registers in compatibility mode.
*/
#define ADBUFE ADEMDR0
#define ADBUF1 ADEMDR4
#define ADBUF2 ADEMDR8
#define ADEMUBUFE ADEMDR14
#define ADEMUBUF1 ADDR15
#define ADEMUBUF2 ADEMDR15
__IO_REG16( ADINR, 0xfff7f09e,__READ_WRITE);
__IO_REG16_BIT(ADCPCR, 0xfff7f0a2,__READ_WRITE,__adcpcr_bits);
__IO_REG16_BIT(ADSAMPEV, 0xfff7f0b2,__READ_WRITE,__adsampev_bits);
__IO_REG16_BIT(ADSAMP1, 0xfff7f0b6,__READ_WRITE,__adsamp1_bits);
__IO_REG16_BIT(ADSAMP2, 0xfff7f0ba,__READ_WRITE,__adsamp2_bits);
__IO_REG16_BIT(ADBCR1, 0xfff7f0be,__READ_WRITE,__adbcr1_bits);
__IO_REG16_BIT(ADBCR2, 0xfff7f0c2,__READ_WRITE,__adbcr2_bits);
__IO_REG16_BIT(ADBCR3, 0xfff7f0c6,__READ_WRITE,__adbcr3_bits);
__IO_REG16_BIT(ADBUFST, 0xfff7f0ca,__READ_WRITE,__adbufst_bits);
__IO_REG16_BIT(ADTHREV, 0xfff7f0ce,__READ_WRITE,__adthrev_bits);
__IO_REG16_BIT(ADTHRG1, 0xfff7f0d2,__READ_WRITE,__adthrg1_bits);
__IO_REG16_BIT(ADTHRG2, 0xfff7f0d6,__READ_WRITE,__adthrg2_bits);
__IO_REG16_BIT(ADEVTSRC, 0xfff7f0da,__READ_WRITE,__adevtsrc_bits);
/***************************************************************************
**
** ECP
**
***************************************************************************/
__IO_REG16_BIT(ECPCTRL, 0xfff7ef02,__READ_WRITE,__ecpctrl_bits);
/***************************************************************************
**
** EBM
**
***************************************************************************/
__IO_REG8( EBDMACR,0xfff7ed03,__READ_WRITE);
__IO_REG8_BIT(EBRWCR, 0xfff7ed07,__READ_WRITE, __ebrwcr_bits);
__IO_REG8_BIT(EBACR1, 0xfff7ed0b,__READ_WRITE, __ebacr1_bits);
__IO_REG8( EBDCR, 0xfff7ed0f,__READ_WRITE);
__IO_REG8( EBADCR, 0xfff7ed13,__READ_WRITE);
__IO_REG8( EBACR2, 0xfff7ed17,__READ_WRITE);
__IO_REG8( EBACR3, 0xfff7ed1b,__READ_WRITE);
__IO_REG8_BIT(EBMCR1, 0xfff7ed1f,__READ_WRITE, __ebmcr1_bits);
/***************************************************************************
**
** GIO
**
***************************************************************************/
__IO_REG32_BIT(GIOPWDN, 0xfff7ec00,__READ_WRITE,__giopwdn_bits);
__IO_REG32_BIT(GIOENA1, 0xfff7ec04,__READ_WRITE,__gioena1_bits);
__IO_REG32_BIT(GIOPOL1, 0xfff7ec08,__READ_WRITE,__giopol1_bits);
__IO_REG32_BIT(GIOFLG1, 0xfff7ec0c,__READ_WRITE,__gioflg1_bits);
__IO_REG32_BIT(GIOPRY1, 0xfff7ec10,__READ_WRITE,__giopry1_bits);
__IO_REG32_BIT(GIOOFFA, 0xfff7ec14,__READ_WRITE,__giooffa_bits);
__IO_REG32_BIT(GIOEMUA, 0xfff7ec18,__READ_WRITE,__gioemua_bits);
__IO_REG32_BIT(GIOOFFB, 0xfff7ec1c,__READ_WRITE,__giooffb_bits);
__IO_REG32_BIT(GIOEMUB, 0xfff7ec20,__READ_WRITE,__gioemub_bits);
__IO_REG32_BIT(GIODIRA, 0xfff7ec24,__READ_WRITE,__giodir_bits);
__IO_REG32_BIT(GIODINA, 0xfff7ec28,__READ_WRITE,__giodin_bits);
__IO_REG32_BIT(GIODOUTA, 0xfff7ec2c,__READ_WRITE,__giodout_bits);
__IO_REG32_BIT(GIODSETA, 0xfff7ec30,__READ_WRITE,__giodset_bits);
__IO_REG32_BIT(GIODCLRA, 0xfff7ec34,__READ_WRITE,__giodclr_bits);
__IO_REG32_BIT(GIODIRB, 0xfff7ec38,__READ_WRITE,__giodir_bits);
__IO_REG32_BIT(GIODINB, 0xfff7ec3c,__READ_WRITE,__giodin_bits);
__IO_REG32_BIT(GIODOUTB, 0xfff7ec40,__READ_WRITE,__giodout_bits);
__IO_REG32_BIT(GIODSETB, 0xfff7ec44,__READ_WRITE,__giodset_bits);
__IO_REG32_BIT(GIODCLRB, 0xfff7ec48,__READ_WRITE,__giodclr_bits);
/***************************************************************************
**
** SCC
**
***************************************************************************/
__IO_REG32( CANME_SCC, 0xfff7e000,__READ_WRITE);
__IO_REG32( CANMD_SCC, 0xfff7e004,__READ_WRITE);
__IO_REG32( CANTRS_SCC, 0xfff7e008,__READ_WRITE);
__IO_REG32( CANTRR_SCC, 0xfff7e00c,__READ_WRITE);
__IO_REG32( CANTA_SCC, 0xfff7e010,__READ_WRITE);
__IO_REG32( CANAA_SCC, 0xfff7e014,__READ_WRITE);
__IO_REG32( CANRMP_SCC, 0xfff7e018,__READ_WRITE);
__IO_REG32( CANRML_SCC, 0xfff7e01c,__READ_WRITE);
__IO_REG32( CANRFP_SCC, 0xfff7e020,__READ_WRITE);
__IO_REG32_BIT(CANGAM_SCC, 0xfff7e024,__READ_WRITE,__cangam_bits);
__IO_REG32_BIT(CANMC_SCC_SCC, 0xfff7e028,__READ_WRITE,__canmc_bits);
__IO_REG32_BIT(CANBTC_SCC, 0xfff7e02c,__READ_WRITE,__canbtc_bits);
__IO_REG32_BIT(CANES_SCC, 0xfff7e030,__READ_WRITE,__canes_bits);
__IO_REG32_BIT(CANTEC_SCC, 0xfff7e034,__READ_WRITE,__cantec_bits);
__IO_REG32_BIT(CANREC_SCC, 0xfff7e038,__READ_WRITE,__canrec_bits);
__IO_REG32_BIT(CANGIF0_SCC, 0xfff7e03c,__READ_WRITE,__cangif_bits);
__IO_REG32_BIT(CANGIM_SCC, 0xfff7e040,__READ_WRITE,__cangim_bits);
__IO_REG32_BIT(CANGIF1_SCC, 0xfff7e044,__READ_WRITE,__cangif_bits);
__IO_REG32( CANMIM_SCC, 0xfff7e048,__READ_WRITE);
__IO_REG32( CANMIL_SCC, 0xfff7e04c,__READ_WRITE);
__IO_REG32( CANOPC_SCC, 0xfff7e050,__READ_WRITE);
__IO_REG32_BIT(CANTIOC_SCC, 0xfff7e054,__READ_WRITE,__cantioc_bits);
__IO_REG32_BIT(CANRIOC_SCC, 0xfff7e058,__READ_WRITE,__canrioc_bits);
/***************************************************************************
**
** SCC RAM
**
***************************************************************************/
__IO_REG32_BIT( CANMID0_SCC , 0xfff7dc00,__READ_WRITE, __mid_bits); /* Message identifier */
__IO_REG32_BIT( CANMID1_SCC , 0xfff7dc10,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID2_SCC , 0xfff7dc20,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID3_SCC , 0xfff7dc30,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID4_SCC , 0xfff7dc40,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID5_SCC , 0xfff7dc50,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID6_SCC , 0xfff7dc60,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID7_SCC , 0xfff7dc70,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID8_SCC , 0xfff7dc80,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID9_SCC , 0xfff7dc90,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID10_SCC, 0xfff7dca0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID11_SCC, 0xfff7dcb0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID12_SCC, 0xfff7dcc0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID13_SCC, 0xfff7dcd0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID14_SCC, 0xfff7dce0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID15_SCC, 0xfff7dcf0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMCF0_SCC , 0xfff7dc04,__READ_WRITE, __mcf_bits); /* Message control field */
__IO_REG32_BIT( CANMCF1_SCC , 0xfff7dc14,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF2_SCC , 0xfff7dc24,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF3_SCC , 0xfff7dc34,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF4_SCC , 0xfff7dc44,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF5_SCC , 0xfff7dc54,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF6_SCC , 0xfff7dc64,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF7_SCC , 0xfff7dc74,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF8_SCC , 0xfff7dc84,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF9_SCC , 0xfff7dc94,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF10_SCC, 0xfff7dca4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF11_SCC, 0xfff7dcb4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF12_SCC, 0xfff7dcc4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF13_SCC, 0xfff7dcd4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF14_SCC, 0xfff7dce4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF15_SCC, 0xfff7dcf4,__READ_WRITE, __mcf_bits);
__IO_REG32( CANMDL0_SCC , 0xfff7dc08,__READ_WRITE); /* Message data low word */
__IO_REG32( CANMDL1_SCC , 0xfff7dc18,__READ_WRITE);
__IO_REG32( CANMDL2_SCC , 0xfff7dc28,__READ_WRITE);
__IO_REG32( CANMDL3_SCC , 0xfff7dc38,__READ_WRITE);
__IO_REG32( CANMDL4_SCC , 0xfff7dc48,__READ_WRITE);
__IO_REG32( CANMDL5_SCC , 0xfff7dc58,__READ_WRITE);
__IO_REG32( CANMDL6_SCC , 0xfff7dc68,__READ_WRITE);
__IO_REG32( CANMDL7_SCC , 0xfff7dc78,__READ_WRITE);
__IO_REG32( CANMDL8_SCC , 0xfff7dc88,__READ_WRITE);
__IO_REG32( CANMDL9_SCC , 0xfff7dc98,__READ_WRITE);
__IO_REG32( CANMDL10_SCC, 0xfff7dca8,__READ_WRITE);
__IO_REG32( CANMDL11_SCC, 0xfff7dcb8,__READ_WRITE);
__IO_REG32( CANMDL12_SCC, 0xfff7dcc8,__READ_WRITE);
__IO_REG32( CANMDL13_SCC, 0xfff7dcd8,__READ_WRITE);
__IO_REG32( CANMDL14_SCC, 0xfff7dce8,__READ_WRITE);
__IO_REG32( CANMDL15_SCC, 0xfff7dcf8,__READ_WRITE);
__IO_REG32( CANMDH0_SCC , 0xfff7dc0c,__READ_WRITE); /* Message data high word */
__IO_REG32( CANMDH1_SCC , 0xfff7dc1c,__READ_WRITE);
__IO_REG32( CANMDH2_SCC , 0xfff7dc2c,__READ_WRITE);
__IO_REG32( CANMDH3_SCC , 0xfff7dc3c,__READ_WRITE);
__IO_REG32( CANMDH4_SCC , 0xfff7dc4c,__READ_WRITE);
__IO_REG32( CANMDH5_SCC , 0xfff7dc5c,__READ_WRITE);
__IO_REG32( CANMDH6_SCC , 0xfff7dc6c,__READ_WRITE);
__IO_REG32( CANMDH7_SCC , 0xfff7dc7c,__READ_WRITE);
__IO_REG32( CANMDH8_SCC , 0xfff7dc8c,__READ_WRITE);
__IO_REG32( CANMDH9_SCC , 0xfff7dc9c,__READ_WRITE);
__IO_REG32( CANMDH10_SCC, 0xfff7dcac,__READ_WRITE);
__IO_REG32( CANMDH11_SCC, 0xfff7dcbc,__READ_WRITE);
__IO_REG32( CANMDH12_SCC, 0xfff7dccc,__READ_WRITE);
__IO_REG32( CANMDH13_SCC, 0xfff7dcdc,__READ_WRITE);
__IO_REG32( CANMDH14_SCC, 0xfff7dcec,__READ_WRITE);
__IO_REG32( CANMDH15_SCC, 0xfff7dcfc,__READ_WRITE);
#define SCC_RAM_OFFSET 0xFFF7DC00
/***************************************************************************
**
** HECC 1
**
***************************************************************************/
__IO_REG32( CANME_HECC1, 0xfff7e800,__READ_WRITE);
__IO_REG32( CANMD_HECC1, 0xfff7e804,__READ_WRITE);
__IO_REG32( CANTRS_HECC1, 0xfff7e808,__READ_WRITE);
__IO_REG32( CANTRR_HECC1, 0xfff7e80c,__READ_WRITE);
__IO_REG32( CANTA_HECC1, 0xfff7e810,__READ_WRITE);
__IO_REG32( CANAA_HECC1, 0xfff7e814,__READ_WRITE);
__IO_REG32( CANRMP_HECC1, 0xfff7e818,__READ_WRITE);
__IO_REG32( CANRML_HECC1, 0xfff7e81c,__READ_WRITE);
__IO_REG32( CANRFP_HECC1, 0xfff7e820,__READ_WRITE);
__IO_REG32_BIT(CANGAM_HECC1, 0xfff7e824,__READ_WRITE,__cangam_bits);
__IO_REG32_BIT(CANMC_HECC1, 0xfff7e828,__READ_WRITE,__canmc_bits);
__IO_REG32_BIT(CANBTC_HECC1, 0xfff7e82c,__READ_WRITE,__canbtc_bits);
__IO_REG32_BIT(CANES_HECC1, 0xfff7e830,__READ_WRITE,__canes_bits);
__IO_REG32_BIT(CANTEC_HECC1, 0xfff7e834,__READ_WRITE,__cantec_bits);
__IO_REG32_BIT(CANREC_HECC1, 0xfff7e838,__READ_WRITE,__canrec_bits);
__IO_REG32_BIT(CANGIF0_HECC1, 0xfff7e83c,__READ_WRITE,__cangif_bits);
__IO_REG32_BIT(CANGIM_HECC1, 0xfff7e840,__READ_WRITE,__cangim_bits);
__IO_REG32_BIT(CANGIF1_HECC1, 0xfff7e844,__READ_WRITE,__cangif_bits);
__IO_REG32( CANMIM_HECC1, 0xfff7e848,__READ_WRITE);
__IO_REG32( CANMIL_HECC1, 0xfff7e84c,__READ_WRITE);
__IO_REG32( CANOPC_HECC1, 0xfff7e850,__READ_WRITE);
__IO_REG32_BIT(CANTIOC_HECC1, 0xfff7e854,__READ_WRITE,__cantioc_bits);
__IO_REG32_BIT(CANRIOC_HECC1, 0xfff7e858,__READ_WRITE,__canrioc_bits);
__IO_REG32( CANLNT_HECC1, 0xfff7e85c,__READ_WRITE);
__IO_REG32( CANTOC_HECC1, 0xfff7e860,__READ_WRITE);
__IO_REG32( CANTOS_HECC1, 0xfff7e864,__READ_WRITE);
/***************************************************************************
**
** HECC 1 RAM
**
***************************************************************************/
__IO_REG32_BIT( CANMID0_HECC1 , 0xfff7e400,__READ_WRITE, __mid_bits); /* Message identifier */
__IO_REG32_BIT( CANMID1_HECC1 , 0xfff7e410,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID2_HECC1 , 0xfff7e420,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID3_HECC1 , 0xfff7e430,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID4_HECC1 , 0xfff7e440,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID5_HECC1 , 0xfff7e450,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID6_HECC1 , 0xfff7e460,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID7_HECC1 , 0xfff7e470,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID8_HECC1 , 0xfff7e480,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID9_HECC1 , 0xfff7e490,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID10_HECC1, 0xfff7e4a0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID11_HECC1, 0xfff7e4b0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID12_HECC1, 0xfff7e4c0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID13_HECC1, 0xfff7e4d0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID14_HECC1, 0xfff7e4e0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID15_HECC1, 0xfff7e4f0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMCF0_HECC1 , 0xfff7e404,__READ_WRITE, __mcf_bits); /* Message control field */
__IO_REG32_BIT( CANMCF1_HECC1 , 0xfff7e414,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF2_HECC1 , 0xfff7e424,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF3_HECC1 , 0xfff7e434,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF4_HECC1 , 0xfff7e444,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF5_HECC1 , 0xfff7e454,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF6_HECC1 , 0xfff7e464,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF7_HECC1 , 0xfff7e474,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF8_HECC1 , 0xfff7e484,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF9_HECC1 , 0xfff7e494,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF10_HECC1, 0xfff7e4a4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF11_HECC1, 0xfff7e4b4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF12_HECC1, 0xfff7e4c4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF13_HECC1, 0xfff7e4d4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF14_HECC1, 0xfff7e4e4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF15_HECC1, 0xfff7e4f4,__READ_WRITE, __mcf_bits);
__IO_REG32( CANMDL0_HECC1 , 0xfff7e408,__READ_WRITE); /* Message data low word */
__IO_REG32( CANMDL1_HECC1 , 0xfff7e418,__READ_WRITE);
__IO_REG32( CANMDL2_HECC1 , 0xfff7e428,__READ_WRITE);
__IO_REG32( CANMDL3_HECC1 , 0xfff7e438,__READ_WRITE);
__IO_REG32( CANMDL4_HECC1 , 0xfff7e448,__READ_WRITE);
__IO_REG32( CANMDL5_HECC1 , 0xfff7e458,__READ_WRITE);
__IO_REG32( CANMDL6_HECC1 , 0xfff7e468,__READ_WRITE);
__IO_REG32( CANMDL7_HECC1 , 0xfff7e478,__READ_WRITE);
__IO_REG32( CANMDL8_HECC1 , 0xfff7e488,__READ_WRITE);
__IO_REG32( CANMDL9_HECC1 , 0xfff7e498,__READ_WRITE);
__IO_REG32( CANMDL10_HECC1, 0xfff7e4a8,__READ_WRITE);
__IO_REG32( CANMDL11_HECC1, 0xfff7e4b8,__READ_WRITE);
__IO_REG32( CANMDL12_HECC1, 0xfff7e4c8,__READ_WRITE);
__IO_REG32( CANMDL13_HECC1, 0xfff7e4d8,__READ_WRITE);
__IO_REG32( CANMDL14_HECC1, 0xfff7e4e8,__READ_WRITE);
__IO_REG32( CANMDL15_HECC1, 0xfff7e4f8,__READ_WRITE);
__IO_REG32( CANMDH0_HECC1 , 0xfff7e40c,__READ_WRITE); /* Message data high word */
__IO_REG32( CANMDH1_HECC1 , 0xfff7e41c,__READ_WRITE);
__IO_REG32( CANMDH2_HECC1 , 0xfff7e42c,__READ_WRITE);
__IO_REG32( CANMDH3_HECC1 , 0xfff7e43c,__READ_WRITE);
__IO_REG32( CANMDH4_HECC1 , 0xfff7e44c,__READ_WRITE);
__IO_REG32( CANMDH5_HECC1 , 0xfff7e45c,__READ_WRITE);
__IO_REG32( CANMDH6_HECC1 , 0xfff7e46c,__READ_WRITE);
__IO_REG32( CANMDH7_HECC1 , 0xfff7e47c,__READ_WRITE);
__IO_REG32( CANMDH8_HECC1 , 0xfff7e48c,__READ_WRITE);
__IO_REG32( CANMDH9_HECC1 , 0xfff7e49c,__READ_WRITE);
__IO_REG32( CANMDH10_HECC1, 0xfff7e4ac,__READ_WRITE);
__IO_REG32( CANMDH11_HECC1, 0xfff7e4bc,__READ_WRITE);
__IO_REG32( CANMDH12_HECC1, 0xfff7e4cc,__READ_WRITE);
__IO_REG32( CANMDH13_HECC1, 0xfff7e4dc,__READ_WRITE);
__IO_REG32( CANMDH14_HECC1, 0xfff7e4ec,__READ_WRITE);
__IO_REG32( CANMDH15_HECC1, 0xfff7e4fc,__READ_WRITE);
#define HECC1_RAM_OFFSET 0xFFF7e400
/***************************************************************************
**
** HECC 2
**
***************************************************************************/
__IO_REG32( CANME_HECC2, 0xfff7ea00,__READ_WRITE);
__IO_REG32( CANMD_HECC2, 0xfff7ea04,__READ_WRITE);
__IO_REG32( CANTRS_HECC2, 0xfff7ea08,__READ_WRITE);
__IO_REG32( CANTRR_HECC2, 0xfff7ea0c,__READ_WRITE);
__IO_REG32( CANTA_HECC2, 0xfff7ea10,__READ_WRITE);
__IO_REG32( CANAA_HECC2, 0xfff7ea14,__READ_WRITE);
__IO_REG32( CANRMP_HECC2, 0xfff7ea18,__READ_WRITE);
__IO_REG32( CANRML_HECC2, 0xfff7ea1c,__READ_WRITE);
__IO_REG32( CANRFP_HECC2, 0xfff7ea20,__READ_WRITE);
__IO_REG32_BIT(CANGAM_HECC2, 0xfff7ea24,__READ_WRITE,__cangam_bits);
__IO_REG32_BIT(CANMC_HECC2, 0xfff7ea28,__READ_WRITE,__canmc_bits);
__IO_REG32_BIT(CANBTC_HECC2, 0xfff7ea2c,__READ_WRITE,__canbtc_bits);
__IO_REG32_BIT(CANES_HECC2, 0xfff7ea30,__READ_WRITE,__canes_bits);
__IO_REG32_BIT(CANTEC_HECC2, 0xfff7ea34,__READ_WRITE,__cantec_bits);
__IO_REG32_BIT(CANREC_HECC2, 0xfff7ea38,__READ_WRITE,__canrec_bits);
__IO_REG32_BIT(CANGIF0_HECC2, 0xfff7ea3c,__READ_WRITE,__cangif_bits);
__IO_REG32_BIT(CANGIM_HECC2, 0xfff7ea40,__READ_WRITE,__cangim_bits);
__IO_REG32_BIT(CANGIF1_HECC2, 0xfff7ea44,__READ_WRITE,__cangif_bits);
__IO_REG32( CANMIM_HECC2, 0xfff7ea48,__READ_WRITE);
__IO_REG32( CANMIL_HECC2, 0xfff7ea4c,__READ_WRITE);
__IO_REG32( CANOPC_HECC2, 0xfff7ea50,__READ_WRITE);
__IO_REG32_BIT(CANTIOC_HECC2, 0xfff7ea54,__READ_WRITE,__cantioc_bits);
__IO_REG32_BIT(CANRIOC_HECC2, 0xfff7ea58,__READ_WRITE,__canrioc_bits);
__IO_REG32( CANLNT_HECC2, 0xfff7ea5c,__READ_WRITE);
__IO_REG32( CANTOC_HECC2, 0xfff7ea60,__READ_WRITE);
__IO_REG32( CANTOS_HECC2, 0xfff7ea64,__READ_WRITE);
/***************************************************************************
**
** HECC 2 RAM
**
***************************************************************************/
__IO_REG32_BIT( CANMID0_HECC2 , 0xfff7e600,__READ_WRITE, __mid_bits); /* Message identifier */
__IO_REG32_BIT( CANMID1_HECC2 , 0xfff7e610,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID2_HECC2 , 0xfff7e620,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID3_HECC2 , 0xfff7e630,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID4_HECC2 , 0xfff7e640,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID5_HECC2 , 0xfff7e650,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID6_HECC2 , 0xfff7e660,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID7_HECC2 , 0xfff7e670,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID8_HECC2 , 0xfff7e680,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID9_HECC2 , 0xfff7e690,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID10_HECC2, 0xfff7e6a0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID11_HECC2, 0xfff7e6b0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID12_HECC2, 0xfff7e6c0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID13_HECC2, 0xfff7e6d0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID14_HECC2, 0xfff7e6e0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMID15_HECC2, 0xfff7e6f0,__READ_WRITE, __mid_bits);
__IO_REG32_BIT( CANMCF0_HECC2 , 0xfff7e604,__READ_WRITE, __mcf_bits); /* Message control field */
__IO_REG32_BIT( CANMCF1_HECC2 , 0xfff7e614,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF2_HECC2 , 0xfff7e624,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF3_HECC2 , 0xfff7e634,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF4_HECC2 , 0xfff7e644,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF5_HECC2 , 0xfff7e654,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF6_HECC2 , 0xfff7e664,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF7_HECC2 , 0xfff7e674,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF8_HECC2 , 0xfff7e684,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF9_HECC2 , 0xfff7e694,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF10_HECC2, 0xfff7e6a4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF11_HECC2, 0xfff7e6b4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF12_HECC2, 0xfff7e6c4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT( CANMCF13_HECC2, 0xfff7e6d4,__READ_WRITE, __mcf_bits);
__IO_REG32_BIT(