###########################################################################
//
// FILE: tms470r1_bit_definitions.h
//
// TITLE: TMS470R1 Device Bit Definitions.
//
//###########################################################################
//
// Ver | dd mmm yyyy | Who | Description of changes
// ======|=============|======|==============================================
// 0.01 | 14 Dec 2004 | J.M. | Created
// 0.06 | 14 Jan 2005 | J.M. | Added Definitions
// | | |
// The following signals were inconfict with other desigantions andd required
// unique names which included the module.
//
// HETGCR_POWERDOWN CAN_TXDIR CAN_RXDIR
// SCI_POWERDOWN C2_TXDIR C2_RXDIR
// SPI_POWERDOWN
//
// Texas Instruments, Inc
// Copyright Texas Instruments 2005 . All rights reserved.
//###########################################################################
#ifndef tms470r1a256_bit_definitions_H
#define tms470r1a256_bit_definitions_H
#ifdef __cplusplus
extern "C" {
#endif
//***********************************************************************************
// C2SIA Module and C2SIB Module Same definitions for both modules
//-------------------------------------------------
// C2SIA C2SIAISR Interrupt Status Register bit definitions
//
// C2SIAISR_BITS
#define RBFIF ((unsigned int) 0x1 << 0) // 0 Receive buffer full interrupt flag
#define BRKIF ((unsigned int) 0x1 << 1) // 1 Receive break interrupt flag
#define RCCIF ((unsigned int) 0x1 << 2) // 2 Receive completion code interrupt flag
#define RXOIF ((unsigned int) 0x1 << 3) // 3 Receive over-run interrupt flag
#define TXUOIF ((unsigned int) 0x1 << 4) // 4 Transmit under-run/over-run interrupt flag
#define TBEIF ((unsigned int) 0x1 << 5) // 5 Transmit buffer empty interrupt flag
#define TIDLIF ((unsigned int) 0x1 << 6) // 6 Transmit idle interrupt flag
#define ARBIF ((unsigned int) 0x1 << 7) // 7 Transmit arbitration lost interrupt flag
//-------------------------------------------------
// C2SIA C2SIAICR Interrupt Control Register bit definitions
//
// C2SIAICR_BITS
#define RBFIE ((unsigned int) 0x1 << 0) // 0 Receive buffer full interrupt enable
#define BRKIE ((unsigned int) 0x1 << 1) // 1 Receive break interrupt enable
#define RCCIE ((unsigned int) 0x1 << 2) // 2 Receive completion code interrupt enable
#define RXOIE ((unsigned int) 0x1 << 3) // 3 Receive over-run interrupt enable
#define TXUOIE ((unsigned int) 0x1 << 4) // 4 Transmit under-run/over-run interrupt enable
#define TBEIE ((unsigned int) 0x1 << 5) // 5 Transmit buffer empty interrupt enable
#define TIDLIE ((unsigned int) 0x1 << 6) // 6 Transmit idle interrupt enable
#define ARBIE ((unsigned int) 0x1 << 7) // 7 Transmit arbitration lost interrupt enable
//-------------------------------------------------
// C2SIA C2SIAGSR Global Status Register bit definitions
//
// C2SIAGSR_BITS
#define WAKE ((unsigned int) 0x1 << 0) // 0 Wake-up from low power mode status flag
#define NOISE ((unsigned int) 0x1 << 1) // 1 Noise detected on C2Sia data link flag
#define SHORTGND ((unsigned int) 0x1 << 2) // 2 Short to ground detected
#define IDLE ((unsigned int) 0x1 << 3) // 3 Data link idle flag
#define RIFR ((unsigned int) 0x1 << 4) // 4 Receive In-frame response control bit
#define TXERROR ((unsigned int) 0x1 << 5) // 5 Transmission error found
//-------------------------------------------------
// C2SIA C2SIAGCR Global Control Register bit definitions
//
// C2SIAGCR_BITS
#define ENWAKE ((unsigned int) 0x1 << 0) // 0 Wake-up enable
#define TIFR ((unsigned int) 0x1 << 1) // 1 Transmit in-frame response control bit
#define TBRK ((unsigned int) 0x1 << 2) // 2 Transmit break sequence control bit
#define TXRESET ((unsigned int) 0x1 << 3) // 3 Transmit reset
#define NBPOL ((unsigned int) 0x1 << 4) // 4 Normalization bit polarity control bit
#define T2IFR ((unsigned int) 0x1 << 5) // 5 Type 2 in-frame response control bit
#define MODE4X ((unsigned int) 0x1 << 6) // 6 4X mode control bit
#define CRCDIS ((unsigned int) 0x1 << 7) // 7 CRC disable
//-------------------------------------------------
// C2SIA C2SIACCSR Completion Code Status Register bit definitions
//
// C2SIACCSR_BITS
#define IFRCRC ((unsigned int) 0x1 << 0) // 0 Receiver in-frame response with a CRC flag
#define IFR ((unsigned int) 0x1 << 1) // 1 Receiver in-frame response flag
#define BREAK ((unsigned int) 0x1 << 2) // 2 Receiver break sequence flag
#define XMITOK ((unsigned int) 0x1 << 3) // 3 Received transmitted message and transmit was OK flag
#define CRCERR ((unsigned int) 0x1 << 4) // 4 Received message CRC error flag
#define BYTERR ((unsigned int) 0x1 << 5) // 5 Received an incomplete byte error flag
#define BITERR ((unsigned int) 0x1 << 6) // 6 Received an improperly timed bit error flag
#define ROVR ((unsigned int) 0x1 << 7) // 7 Receive completion code over-run flag
//-------------------------------------------------
// C2SIA C2SIACTR Completion Code Status Register bit definitions
//
// C2SIACTR_BITS
#define LPM ((unsigned int) 0x1 << 0) // 0 Low power mode
#define ESPEN ((unsigned int) 0x1 << 1) // 1 Emulator suspend
#define RXDMAEN ((unsigned int) 0x1 << 2) // 2 Receive DMA enable
#define TXDMAEN ((unsigned int) 0x1 << 3) // 3 Transmit DMA enable
#define SOFX ((unsigned int) 0x1 << 4) // 4 SOF behavior
#define LPEN ((unsigned int) 0x1 << 5) // 5 Loopback enable
#define CALEN ((unsigned int) 0x1 << 6) // 6 Auto calibration enable
#define LONGBRK ((unsigned int) 0x1 << 7) // 7 Long break symbol length
//-------------------------------------------------
// C2SIA C2SIAPC1 Pin Control Register 1 bit definitions
//
// C2SIAPC1_BITS
#define LPDIR ((unsigned int) 0x1 << 0) // 0 Loopback pin direction select
#define C2_RXDIR ((unsigned int) 0x1 << 1) // 1 Receive pin direction select
#define C2_TXDIR ((unsigned int) 0x1 << 2) // 2 Transmit pin direction select
#define LPFUN ((unsigned int) 0x1 << 3) // 3 Loopback pin function select
#define RXFUN ((unsigned int) 0x1 << 4) // 4 Receive pin function select
#define TXFUN ((unsigned int) 0x1 << 5) // 5 Transmit pin function select
#define RXPOL ((unsigned int) 0x1 << 6) // 6 Receive pin polarity select
#define TXPOL ((unsigned int) 0x1 << 7) // 7 Transmit pin polarity select
//-------------------------------------------------
// C2SIA C2SIAPC2 Pin Control Register 2 bit definitions
//
// C2SIAPC2_BITS
#define LPDOUT ((unsigned int) 0x1 << 0) // 0 Loopback data out
#define RXDOUT ((unsigned int) 0x1 << 1) // 1 Receive data out
#define TXDOUT ((unsigned int) 0x1 << 2) // 2 Transmit data out
//-------------------------------------------------
// C2SIA C2SIAPC3 Pin Control Register 3 bit definitions
//
// C2SIAPC3_BITS
#define LPDIN ((unsigned int) 0x1 << 0) // 0 Loopback data in
#define RXDIN ((unsigned int) 0x1 << 1) // 1 Receive data in
#define TXDIN ((unsigned int) 0x1 << 2) // 2 Transmit data in
//-------------------------------------------------
// C2SIA C2SIACAL Calibration Control Register bit definitions
//
// C2SIACAL_BITS
#define ARBTYPE ((unsigned int) 0x1 << 7) // 7 Arbitration type
//-------------------------------------------------
// C2SIA C2SIABRK Break Status Register bit definitions
//
// C2SIABRK_BITS
#define INBREAK ((unsigned int) 0x1 << 0) // 0 Break status
#define BREAKEND ((unsigned int) 0x1 << 1) // 1 End of break found
//******************************************************************************************
// GIO Module
//-------------------------------------------------
// GIO GIOPWDN GIO Power Down Register bit definitions
//
// GIOPWDN_BITS
#define GIOPWDN ((unsigned int) 0x1 << 0) // 0 GIO power down
//-------------------------------------------------
// GIO GIOENA1, GIOPOL1, GIOFLG1 and GIOPRY1 GIO Interrupt Enable Register bit definitions
//
#define A0 ((unsigned int) 0x1 << 0) // 0 Pin interrupt enable
#define A1 ((unsigned int) 0x1 << 1) // 1 Pin interrupt enable
#define A2 ((unsigned int) 0x1 << 2) // 2 Pin interrupt enable
#define A3 ((unsigned int) 0x1 << 3) // 3 Pin interrupt enable
#define A4 ((unsigned int) 0x1 << 4) // 4 Pin interrupt enable
#define A5 ((unsigned int) 0x1 << 5) // 5 Pin interrupt enable
#define A6 ((unsigned int) 0x1 << 6) // 6 Pin interrupt enable
#define A7 ((unsigned int) 0x1 << 7) // 7 Pin interrupt enable
#define B0 ((unsigned int) 0x1 << 8) // 8 Pin interrupt enable
#define B1 ((unsigned int) 0x1 << 9) // 9 Pin interrupt enable
#define B2 ((unsigned int) 0x1 << 10) // 10 Pin interrupt enable
#define B3 ((unsigned int) 0x1 << 11) // 11 Pin interrupt enable
#define B4 ((unsigned int) 0x1 << 12) // 12 Pin interrupt enable
#define B5 ((unsigned int) 0x1 << 13) // 13 Pin interrupt enable
#define B6 ((unsigned int) 0x1 << 14) // 14 Pin interrupt enable
#define B7 ((unsigned int) 0x1 << 15) // 15 Pin interrupt enable
#define C0 ((unsigned int) 0x1 << 16) // 16 Pin interrupt enable
#define C1 ((unsigned int) 0x1 << 17) // 17 Pin interrupt enable
#define C2 ((unsigned int) 0x1 << 18) // 18 Pin interrupt enable
#define C3 ((unsigned int) 0x1 << 19) // 19 Pin interrupt enable
#define C4 ((unsigned int) 0x1 << 20) // 20 Pin interrupt enable
#define C5 ((unsigned int) 0x1 << 21) // 21 Pin interrupt enable
#define C6 ((unsigned int) 0x1 << 22) // 22 Pin interrupt enable
#define C7 ((unsigned int) 0x1 << 23) // 23 Pin interrupt enable
#define D0 ((unsigned int) 0x1 << 24) // 24 Pin interrupt enable
#define D1 ((unsigned int) 0x1 << 25) // 25 Pin interrupt enable
#define D2 ((unsigned int) 0x1 << 26) // 26 Pin interrupt enable
#define D3 ((unsigned int) 0x1 << 27) // 27 Pin interrupt enable
#define D4 ((unsigned int) 0x1 << 28) // 28 Pin interrupt enable
#define D5 ((unsigned int) 0x1 << 29) // 29 Pin interrupt enable
#define D6 ((unsigned int) 0x1 << 30) // 30 Pin interrupt enable
#define D7 ((unsigned int) 0x1 << 31) // 31 Pin interrupt enable
//-------------------------------------------------
// GIO GIODIRx , GIODINx, GIODOUTx ,GIODSETx and GIODCLRA GIO Data Direction Register bit definitions
//
#define X0 ((unsigned int) 0x1 << 0) // 0 Port x, pin 0
#define X1 ((unsigned int) 0x1 << 1) // 1 Port x, pin 1
#define X2 ((unsigned int) 0x1 << 2) // 2 Port x, pin 2
#define X3 ((unsigned int) 0x1 << 3) // 3 Port x, pin 3
#define X4 ((unsigned int) 0x1 << 4) // 4 Port x, pin 4
#define X5 ((unsigned int) 0x1 << 5) // 5 Port x, pin 5
#define X6 ((unsigned int) 0x1 << 6) // 6 Port x, pin 6
#define X7 ((unsigned int) 0x1 << 7) // 7 Port x, pin 7
//-------------------------------------------------
// GIO GIOENA2, GIOPOL2, GIOFLG2 and GIOPRY2 GIO Interrupt Enable Register bit definitions
//
#define E0 ((unsigned int) 0x1 << 0) // 0 Pin interrupt enable
#define E1 ((unsigned int) 0x1 << 1) // 1 Pin interrupt enable
#define E2 ((unsigned int) 0x1 << 2) // 2 Pin interrupt enable
#define E3 ((unsigned int) 0x1 << 3) // 3 Pin interrupt enable
#define E4 ((unsigned int) 0x1 << 4) // 4 Pin interrupt enable
#define E5 ((unsigned int) 0x1 << 5) // 5 Pin interrupt enable
#define E6 ((unsigned int) 0x1 << 6) // 6 Pin interrupt enable
#define E7 ((unsigned int) 0x1 << 7) // 7 Pin interrupt enable
#define F0 ((unsigned int) 0x1 << 8) // 8 Pin interrupt enable
#define F1 ((unsigned int) 0x1 << 9) // 9 Pin interrupt enable
#define F2 ((unsigned int) 0x1 << 10) // 10 Pin interrupt enable
#define F3 ((unsigned int) 0x1 << 11) // 11 Pin interrupt enable
#define F4 ((unsigned int) 0x1 << 12) // 12 Pin interrupt enable
#define F5 ((unsigned int) 0x1 << 13) // 13 Pin interrupt enable
#define F6 ((unsigned int) 0x1 << 14) // 14 Pin interrupt enable
#define F7 ((unsigned int) 0x1 << 15) // 15 Pin interrupt enable
#define G0 ((unsigned int) 0x1 << 16) // 16 Pin interrupt enable
#define G1 ((unsigned int) 0x1 << 17) // 17 Pin interrupt enable
#define G2 ((unsigned int) 0x1 << 18) // 18 Pin interrupt enable
#define G3 ((unsigned int) 0x1 << 19) // 19 Pin interrupt enable
#define G4 ((unsigned int) 0x1 << 20) // 20 Pin interrupt enable
#define G5 ((unsigned int) 0x1 << 21) // 21 Pin interrupt enable
#define G6 ((unsigned int) 0x1 << 22) // 22 Pin interrupt enable
#define G7 ((unsigned int) 0x1 << 23) // 23 Pin interrupt enable
#define H0 ((unsigned int) 0x1 << 24) // 24 Pin interrupt enable
#define H1 ((unsigned int) 0x1 << 25) // 25 Pin interrupt enable
#define H2 ((unsigned int) 0x1 << 26) // 26 Pin interrupt enable
#define H3 ((unsigned int) 0x1 << 27) // 27 Pin interrupt enable
#define H4 ((unsigned int) 0x1 << 28) // 28 Pin interrupt enable
#define H5 ((unsigned int) 0x1 << 29) // 29 Pin interrupt enable
#define H6 ((unsigned int) 0x1 << 30) // 30 Pin interrupt enable
#define H7 ((unsigned int) 0x1 << 31) // 31 Pin interrupt enable
//-------------------------------------------------
// External Clock Prescaler (ECP) Control Register bit definitions
//
// ECPCTRL_BITS
#define ECPCOS ((unsigned int) 0x1 << 8) // 8 ECP continue on suspend
#define ECPEN ((unsigned int) 0x1 << 15) // 15 ECP enable
//*****************************************************************************************
// HET Module
//-------------------------------------------------
// HET HETGCR Global Configuration Register bit definitions
//
// HETGCR_BITS
#define ON ((unsigned int) 0x1 << 0) // 0 HET turn on/off
#define IGNORE_SUSPEND ((unsigned int) 0x1 << 1) // 1 Ignore suspend flag
#define DEBUG_STATUS ((unsigned int) 0x1 << 2) // 2 Debug status flag
#define ACCESS64 ((unsigned int) 0x1 << 8) // 8 64-bit access
#define CLK_MASTER ((unsigned int) 0x1 << 16) // 16 Clock master/slave
#define HETGCR_POWERDOWN ((unsigned int) 0x1 << 24) // 24 Power-down mode
//-------------------------------------------------
// HET HETPFR Prescale Factor Register bit definitions
//
// HETPFR_BITS
#define HRPRES_FACTOR_1 ((unsigned int) 0x0 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_2 ((unsigned int) 0x1 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_3 ((unsigned int) 0x2 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_4 ((unsigned int) 0x3 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_5 ((unsigned int) 0x4 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_6 ((unsigned int) 0x5 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_7 ((unsigned int) 0x6 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_8 ((unsigned int) 0x7 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_9 ((unsigned int) 0x8 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_10 ((unsigned int) 0x9 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_11 ((unsigned int) 0x0A << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_12 ((unsigned int) 0x0B << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_13 ((unsigned int) 0x0C << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_14 ((unsigned int) 0x0D << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_15 ((unsigned int) 0x0E << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_16 ((unsigned int) 0x0F << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_17 ((unsigned int) 0x10 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_18 ((unsigned int) 0x11 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_19 ((unsigned int) 0x12 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_20 ((unsigned int) 0x13 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_21 ((unsigned int) 0x14 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_22 ((unsigned int) 0x15 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_23 ((unsigned int) 0x16 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_24 ((unsigned int) 0x17 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_25 ((unsigned int) 0x18 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_26 ((unsigned int) 0x19 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_27 ((unsigned int) 0x1A << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_28 ((unsigned int) 0x1B << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_29 ((unsigned int) 0x1C << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_30 ((unsigned int) 0x1D << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_31 ((unsigned int) 0x1E << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_32 ((unsigned int) 0x1F << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_33 ((unsigned int) 0x20 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_34 ((unsigned int) 0x21 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_35 ((unsigned int) 0x22 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_36 ((unsigned int) 0x23 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_37 ((unsigned int) 0x24 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_38 ((unsigned int) 0x25 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_39 ((unsigned int) 0x26 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_40 ((unsigned int) 0x27 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_41 ((unsigned int) 0x28 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_42 ((unsigned int) 0x29 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_43 ((unsigned int) 0x2A << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_44 ((unsigned int) 0x2B << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_45 ((unsigned int) 0x2C << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_46 ((unsigned int) 0x2D << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_47 ((unsigned int) 0x2E << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_48 ((unsigned int) 0x2F << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_49 ((unsigned int) 0x30 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_50 ((unsigned int) 0x31 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_51 ((unsigned int) 0x32 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_52 ((unsigned int) 0x33 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_53 ((unsigned int) 0x34 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_54 ((unsigned int) 0x35 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_55 ((unsigned int) 0x36 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_56 ((unsigned int) 0x37 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_57 ((unsigned int) 0x38 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_58 ((unsigned int) 0x39 << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_59 ((unsigned int) 0x3A << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_60 ((unsigned int) 0x3B << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_61 ((unsigned int) 0x3C << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_62 ((unsigned int) 0x3D << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_63 ((unsigned int) 0x3E << 0) // 5:0 HR prescale factor code
#define HRPRES_FACTOR_64 ((unsigned int) 0x3F << 0) // 5:0 HR prescale factor code
#define LRPRES_FACTOR_1 ((unsigned int) 0x0 << 8) // 10:8 Loop resolution pre-scale factor code
#define LRPRES_FACTOR_2 ((unsigned int) 0x1 << 8) // 10:8 Loop resolution pre-scale factor code
#define LRPRES_FACTOR_4 ((unsigned int) 0x2 << 8) // 10:8 Loop resolution pre-scale factor code
#define LRPRES_FACTOR_8 ((unsigned int) 0x3 << 8) // 10:8 Loop resolution pre-scale factor code
#define LRPRES_FACTOR_16 ((unsigned int) 0x4 << 8) // 10:8 Loop resolution pre-scale factor code
#define LRPRES_FACTOR_32 ((unsigned int) 0x5 << 8) // 10:8 Loop resolution pre-scale factor code
//-------------------------------------------------
// HET HETEXC1 Exception Control Register bit definitions
//
// HETEXC1_BITS
#define PRGM_OVRFL_PRY ((unsigned int) 0x1 << 0) // 0 Program overflow exception priority
#define APCNT_UNDRFL_PRY ((unsigned int) 0x1 << 1) // 1 Angle period counter underflow exception priority
#define APCNT_OVRFL_PRY ((unsigned int) 0x1 << 2) // 2 Angle period counter overflow exception priority
#define PRGM_OVRFL_ENA ((unsigned int) 0x1 << 8) // 8 Program overflow exception enable
#define APCNT_UNDRFL_ENA ((unsigned int) 0x1 << 16) // 16 Angle period counter underflow exception enable
#define APCNT_OVRFL_ENA ((unsigned int) 0x1 << 24) // 24 Angle period counter overflow exception enable
//-------------------------------------------------
// HET HETEXC2 Exception Control Register bit definitions
//
// HETEXC2_BITS
#define PRGM_OVRFL_FLG ((unsigned int) 0x1 << 0) // 0 Program overflow exception flag
#define APCNT_UNDRFL_FLG ((unsigned int) 0x1 << 1) // 1 Angle period counter underflow exception flag
#define APCNT_OVRFL_FLG ((unsigned int) 0x1 << 2) // 2 Angle period counter overflow exception flag
//-------------------------------------------------
// HET HETPRY Interrupt Priority Register bit definitions
//
// HETPRY_BITS
#define HETPRY0 ((unsigned int) 0x1 << 0) // 0 HET interrupt source 0 priority
#define HETPRY1 ((unsigned int) 0x1 << 1) // 1 HET interrupt source 1 priority
#define HETPRY2 ((unsigned int) 0x1 << 2) // 2 HET interrupt source 2 priority
#define HETPRY3 ((unsigned int) 0x1 << 3) // 3 HET interrupt source 3 priority
#define HETPRY4 ((unsigned int) 0x1 << 4) // 4 HET interrupt source 4 priority
#define HETPRY5 ((unsigned int) 0x1 << 5) // 5 HET interrupt source 5 priority
#define HETPRY6 ((unsigned int) 0x1 << 6) // 6 HET interrupt source 6 priority
#define HETPRY7 ((unsigned int) 0x1 << 7) // 7 HET interrupt source 7 priority
#define HETPRY8 ((unsigned int) 0x1 << 8) // 8 HET interrupt source 8 priority
#define HETPRY9 ((unsigned int) 0x1 << 9) // 9 HET interrupt source 9 priority
#define HETPRY10 ((unsigned int) 0x1 << 10) // 10 HET interrupt source 10 priority
#define HETPRY11 ((unsigned int) 0x1 << 11) // 11 HET interrupt source 11 priority
#define HETPRY12 ((unsigned int) 0x1 << 12) // 12 HET interrupt source 12 priority
#define HETPRY13 ((unsigned int) 0x1 << 13) // 13 HET interrupt source 13 priority
#define HETPRY14 ((unsigned int) 0x1 << 14) // 14 HET interrupt source 14 priority
#define HETPRY15 ((unsigned int) 0x1 << 15) // 15 HET interrupt source 15 priority
#define HETPRY16 ((unsigned int) 0x1 << 16) // 16 HET interrupt source 16 priority
#define HETPRY17 ((unsigned int) 0x1 << 17) // 17 HET interrupt source 17 priority
#define HETPRY18 ((unsigned int) 0x1 << 18) // 18 HET interrupt source 18 priority
#define HETPRY19 ((unsigned int) 0x1 << 19) // 19 HET interrupt source 19 priority
#define HETPRY20 ((unsigned int) 0x1 << 20) // 20 HET interrupt source 20 priority
#define HETPRY21 ((unsigned int) 0x1 << 21) // 21 HET interrupt source 21 priority
#define HETPRY22 ((unsigned int) 0x1 << 22) // 22 HET interrupt source 22 priority
#define HETPRY23 ((unsigned int) 0x1 << 23) // 23 HET interrupt source 23 priority
#define HETPRY24 ((unsigned int) 0x1 << 24) // 24 HET interrupt source 24 priority
#define HETPRY25 ((unsigned int) 0x1 << 25) // 25 HET interrupt source 25 priority
#define HETPRY26 ((unsigned int) 0x1 << 26) // 26 HET interrupt source 26 priority
#define HETPRY27 ((unsigned int) 0x1 << 27) // 27 HET interrupt source 27 priority
#define HETPRY28 ((unsigned int) 0x1 << 28) // 28 HET interrupt source 28 priority
#define HETPRY29 ((unsigned int) 0x1 << 29) // 29 HET interrupt source 29 priority
#define HETPRY30 ((unsigned int) 0x1 << 30) // 30 HET interrupt source 30 priority
#define HETPRY31 ((unsigned int) 0x1 << 31) // 31 HET interrupt source 31 priority
//-------------------------------------------------
// HET HETPFLG Interrupt FLAG Register bit definitions
//
// HETFLG_BITS
#define HETFLG0 ((unsigned int) 0x1 << 0) // 0 HET interrupt source 0 flag
#define HETFLG1 ((unsigned int) 0x1 << 1) // 1 HET interrupt source 1 flag
#define HETFLG2 ((unsigned int) 0x1 << 2) // 2 HET interrupt source 2 flag
#define HETFLG3 ((unsigned int) 0x1 << 3) // 3 HET interrupt source 3 flag
#define HETFLG4 ((unsigned int) 0x1 << 4) // 4 HET interrupt source 4 flag
#define HETFLG5 ((unsigned int) 0x1 << 5) // 5 HET interrupt source 5 flag
#define HETFLG6 ((unsigned int) 0x1 << 6) // 6 HET interrupt source 6 flag
#define HETFLG7 ((unsigned int) 0x1 << 7) // 7 HET interrupt source 7 flag
#define HETFLG8 ((unsigned int) 0x1 << 8) // 8 HET interrupt source 8 flag
#define HETFLG9 ((unsigned int) 0x1 << 9) // 9 HET interrupt source 9 flag
#define HETFLG10 ((unsigned int) 0x1 << 10) // 10 HET interrupt source 10 flag
#define HETFLG11 ((unsigned int) 0x1 << 11) // 11 HET interrupt source 11 flag
#define HETFLG12 ((unsigned int) 0x1 << 12) // 12 HET interrupt source 12 flag
#define HETFLG13 ((unsigned int) 0x1 << 13) // 13 HET interrupt source 13 flag
#define HETFLG14 ((unsigned int) 0x1 << 14) // 14 HET interrupt source 14 flag
#define HETFLG15 ((unsigned int) 0x1 << 15) // 15 HET interrupt source 15 flag
#define HETFLG16 ((unsigned int) 0x1 << 16) // 16 HET interrupt source 16 flag
#define HETFLG17 ((unsigned int) 0x1 << 17) // 17 HET interrupt source 17 flag
#define HETFLG18 ((unsigned int) 0x1 << 18) // 18 HET interrupt source 18 flag
#define HETFLG19 ((unsigned int) 0x1 << 19) // 19 HET interrupt source 19 flag
#define HETFLG20 ((unsigned int) 0x1 << 20) // 20 HET interrupt source 20 flag
#define HETFLG21 ((unsigned int) 0x1 << 21) // 21 HET interrupt source 21 flag
#define HETFLG22 ((unsigned int) 0x1 << 22) // 22 HET interrupt source 22 flag
#define HETFLG23 ((unsigned int) 0x1 << 23) // 23 HET interrupt source 23 flag
#define HETFLG24 ((unsigned int) 0x1 << 24) // 24 HET interrupt source 24 flag
#define HETFLG25 ((unsigned int) 0x1 << 25) // 25 HET interrupt source 25 flag
#define HETFLG26 ((unsigned int) 0x1 << 26) // 26 HET interrupt source 26 flag
#define HETFLG27 ((unsigned int) 0x1 << 27) // 27 HET interrupt source 27 flag
#define HETFLG28 ((unsigned int) 0x1 << 28) // 28 HET interrupt source 28 flag
#define HETFLG29 ((unsigned int) 0x1 << 29) // 29 HET interrupt source 29 flag
#define HETFLG30 ((unsigned int) 0x1 << 30) // 30 HET interrupt source 30 flag
#define HETFLG31 ((unsigned int) 0x1 << 31) // 31 HET interrupt source 31 flag
//-------------------------------------------------
// HET HETHRSH HR Share Control Register bit definitions
//
// HETHRSH_BITS
#define HR_SHARE_0_1 ((unsigned int) 0x1 << 0) // 0 HET structure share 0:1
#define HR_SHARE_2_3 ((unsigned int) 0x1 << 1) // 1 HET structure share 2:3
#define HR_SHARE_4_5 ((unsigned int) 0x1 << 2) // 2 HET structure share 4:5
#define HR_SHARE_6_7 ((unsigned int) 0x1 << 3) // 3 HET structure share 6:7
#define HR_SHARE_8_9 ((unsigned int) 0x1 << 4) // 4 HET structure share 8:9
#define HR_SHARE_10_11 ((unsigned int) 0x1 << 5) // 5 HET structure share 10:11
#define HR_SHARE_12_13 ((unsigned int) 0x1 << 6) // 6 HET structure share 12:13
#define HR_SHARE_14_15 ((unsigned int) 0x1 << 7) // 7 HET structure share 14:15
#define HR_SHARE_16_17 ((unsigned int) 0x1 << 8) // 8 HET structure share 16:17
#define HR_SHARE_18_19 ((unsigned int) 0x1 << 9) // 9 HET structure share 18:19
#define HR_SHARE_20_21 ((unsigned int) 0x1 << 10) // 10 HET structure share 20:21
#define HR_SHARE_22_23 ((unsigned int) 0x1 << 11) // 11 HET structure share 22:23
//-------------------------------------------------
// HET HETXOR HR XOR Control Register bit definitions
//
// HETXOR_BITS
#define HR_XOR_SHARE_0_1 ((unsigned int) 0x1 << 0) // 0 HET structure XOR share 0:1
#define HR_XOR_SHARE_2_3 ((unsigned int) 0x1 << 1) // 1 HET structure XOR share 2:3
#define HR_XOR_SHARE_4_5 ((unsigned int) 0x1 << 2) // 2 HET structure XOR share 4:5
#define HR_XOR_SHARE_6_7 ((unsigned int) 0x1 << 3) // 3 HET structure XOR share 6:7
#define HR_XOR_SHARE_8_9 ((unsigned int) 0x1 << 4) // 4 HET structure XOR share 8:9
#define HR_XOR_SHARE_10_11 ((unsigned int) 0x1 << 5) // 5 HET structure XOR share 10:11
#define HR_XOR_SHARE_12_13 ((unsigned int) 0x1 << 6) // 6 HET structure XOR share 12:13
#define HR_XOR_SHARE_14_15 ((unsigned int) 0x1 << 7) // 7 HET structure XOR share 14:15
#define HR_XOR_SHARE_16_17 ((unsigned int) 0x1 << 8) // 8 HET structure XOR share 16:17
#define HR_XOR_SHARE_18_19 ((unsigned int) 0x1 << 9) // 9 HET structure XOR share 18:19
#define HR_XOR_SHARE_20_21 ((unsigned int) 0x1 << 10) // 10 HET structure XOR share 20:21
#define HR_XOR_SHARE_22_23 ((unsigned int) 0x1 << 11) // 11 HET structure XOR share 22:23
//-------------------------------------------------
// HET HETDIR Direction Register bit definitions
//
// HETDIR_BITS
#define HETDIR0 ((unsigned int) 0x1 << 0) // 0 HET pin 0 direction bit
#define HETDIR1 ((unsigned int) 0x1 << 1) // 1 HET pin 1 direction bit
#define HETDIR2 ((unsigned int) 0x1 << 2) // 2 HET pin 2 direction bit
#define HETDIR3 ((unsigned int) 0x1 << 3) // 3 HET pin 3 direction bit
#define HETDIR4 ((unsigned int) 0x1 << 4) // 4 HET pin 4 direction bit
#define HETDIR5 ((unsigned int) 0x1 << 5) // 5 HET pin 5 direction bit
#define HETDIR6 ((unsigned int) 0x1 << 6) // 6 HET pin 6 direction bit
#define HETDIR7 ((unsigned int) 0x1 << 7) // 7 HET pin 7 direction bit
#define HETDIR8 ((unsigned int) 0x1 << 8) // 8 HET pin 8 direction bit
#define HETDIR9 ((unsigned int) 0x1 << 9) // 9 HET pin 9 direction bit
#define HETDIR10 ((unsigned int) 0x1 << 10) // 10 HET pin 10 direction bit
#define HETDIR11 ((unsigned int) 0x1 << 11) // 11 HET pin 11 direction bit
#define HETDIR12 ((unsigned int) 0x1 << 12) // 12 HET pin 12 direction bit
#define HETDIR13 ((unsigned int) 0x1 << 13) // 13 HET pin 13 direction bit
#define HETDIR14 ((unsigned int) 0x1 << 14) // 14 HET pin 14 direction bit
#define HETDIR15 ((unsigned int) 0x1 << 15) // 15 HET pin 15 direction bit
#define HETDIR16 ((unsigned int) 0x1 << 16) // 16 HET pin 16 direction bit
#define HETDIR17 ((unsigned int) 0x1 << 17) // 17 HET pin 17 direction bit
#define HETDIR18 ((unsigned int) 0x1 << 18) // 18 HET pin 18 direction bit
#define HETDIR19 ((unsigned int) 0x1 << 19) // 19 HET pin 19 direction bit
#define HETDIR20 ((unsigned int) 0x1 << 20) // 20 HET pin 20 direction bit
#define HETDIR21 ((unsigned int) 0x1 << 21) // 21 HET pin 21 direction bit
#define HETDIR22 ((unsigned int) 0x1 << 22) // 22 HET pin 22 direction bit
#define HETDIR23 ((unsigned int) 0x1 << 23) // 23 HET pin 23 direction bit
#define HETDIR24 ((unsigned int) 0x1 << 24) // 24 HET pin 24 direction bit
#define HETDIR25 ((unsigned int) 0x1 << 25) // 25 HET pin 25 direction bit
#define HETDIR26 ((unsigned int) 0x1 << 26) // 26 HET pin 26 direction bit
#define HETDIR27 ((unsigned int) 0x1 << 27) // 27 HET pin 27 direction bit
#define HETDIR28 ((unsigned int) 0x1 << 28) // 28 HET pin 28 direction bit
#define HETDIR29 ((unsigned int) 0x1 << 29) // 29 HET pin 29 direction bit
#define HETDIR30 ((unsigned int) 0x1 << 30) // 30 HET pin 30 direction bit
#define HETDIR31 ((unsigned int) 0x1 << 31) // 31 HET pin 31 direction bit
//-------------------------------------------------
// HET HETDIN Data Input Register bit definitions
//
// HETDIN_BITS
#define HETDIN0 ((unsigned int) 0x1 << 0) // 0 HET pin 0 data input bit
#define HETDIN1 ((unsigned int) 0x1 << 1) // 1 HET pin 1 data input bit
#define HETDIN2 ((unsigned int) 0x1 << 2) // 2 HET pin 2 data input bit
#define HETDIN3 ((unsigned int) 0x1 << 3) // 3 HET pin 3 data input bit
#define HETDIN4 ((unsigned int) 0x1 << 4) // 4 HET pin 4 data input bit
#define HETDIN5 ((unsigned int) 0x1 << 5) // 5 HET pin 5 data input bit
#define HETDIN6 ((unsigned int) 0x1 << 6) // 6 HET pin 6 data input bit
#define HETDIN7 ((unsigned int) 0x1 << 7) // 7 HET pin 7 data input bit
#define HETDIN8 ((unsigned int) 0x1 << 8) // 8 HET pin 8 data input bit
#define HETDIN9 ((unsigned int) 0x1 << 9) // 9 HET pin 9 data input bit
#define HETDIN10 ((unsigned int) 0x1 << 10) // 10 HET pin 10 data input bit
#define HETDIN11 ((unsigned int) 0x1 << 11) // 11 HET pin 11 data input bit
#define HETDIN12 ((unsigned int) 0x1 << 12) // 12 HET pin 12 data input bit
#define HETDIN13 ((unsigned int) 0x1 << 13) // 13 HET pin 13 data input bit
#define HETDIN14 ((unsigned int) 0x1 << 14) // 14 HET pin 14 data input bit
#define HETDIN15 ((unsigned int) 0x1 << 15) // 15 HET pin 15 data input bit
#define HETDIN16 ((unsigned int) 0x1 << 16) // 16 HET pin 16 data input bit
#define HETDIN17 ((unsigned int) 0x1 << 17) // 17 HET pin 17 data input bit
#define HETDIN18 ((unsigned int) 0x1 << 18) // 18 HET pin 18 data input bit
#define HETDIN19 ((unsigned int) 0x1 << 19) // 19 HET pin 19 data input bit
#define HETDIN20 ((unsigned int) 0x1 << 20) // 20 HET pin 20 data input bit
#define HETDIN21 ((unsigned int) 0x1 << 21) // 21 HET pin 21 data input bit
#define HETDIN22 ((unsigned int) 0x1 << 22) // 22 HET pin 22 data input bit
#define HETDIN23 ((unsigned int) 0x1 << 23) // 23 HET pin 23 data input bit
#define HETDIN24 ((unsigned int) 0x1 << 24) // 24 HET pin 24 data input bit
#define HETDIN25 ((unsigned int) 0x1 << 25) // 25 HET pin 25 data input bit
#define HETDIN26 ((unsigned int) 0x1 << 26) // 26 HET pin 26 data input bit
#define HETDIN27 ((unsigned int) 0x1 << 27) // 27 HET pin 27 data input bit
#define HETDIN28 ((unsigned int) 0x1 << 28) // 28 HET pin 28 data input bit
#define HETDIN29 ((unsigned int) 0x1 << 29) // 29 HET pin 29 data input bit
#define HETDIN30 ((unsigned int) 0x1 << 30) // 30 HET pin 30 data input bit
#define HETDIN31 ((unsigned int) 0x1 << 31) // 31 HET pin 31 data input bit
//-------------------------------------------------
// HET HETPDOUT Data Output Register bit definitions
//
// HETDOUT_BITS
#define HETDOUT0 ((unsigned int) 0x1 << 0) // 0 HET pin 0 data output bit
#define HETDOUT1 ((unsigned int) 0x1 << 1) // 1 HET pin 1 data output bit
#define HETDOUT